x86_64/cpu: fix cr3 configuration

Previously, the address of the PML4 was being stored in the upper 52
bits of CR3. This is not correct, since the entire CR3 stores the frame
aligned physical address of the PML4, with the lower bits being used for
flags. This means, that in the implementation of the CR3 accessor, the
frame number, not the address, must be stored, since the value type is
designed using bitfields, reserving the upper 52 bits for address
writes.

1 files changed, 5 insertions, 5 deletions

diff --git a/arch/x86_64/include/x86_64/cpu/control_register.hpp b/arch/x86_64/include/x86_64/cpu/control_register.hpp
index 35ffcae..e626b3b 100644
--- a/arch/x86_64/include/x86_64/cpu/control_register.hpp
+++ b/arch/x86_64/include/x86_64/cpu/control_register.hpp
@@ -3,7 +3,7 @@
 
 // IWYU pragma: private, include "x86_64/cpu/registers.hpp"
 
-#include "kapi/memory/address.hpp"
+#include "kapi/memory.hpp"
 
 #include <kstd/ext/bitfield_enum>
 
@@ -182,12 +182,12 @@ namespace teachos::cpu::x86_64
       return memory::physical_address{m_address};
     }
 
-    //! Encode the page aligned physical address of the root page map into this value.
+    //! Encode the frame aligned physical address of the root page map into this value.
     //!
-    //! @param address The page aligned physical address of the root page map.
-    constexpr auto address(memory::physical_address address) -> void
+    //! @param frame The frame containing a PML4.
+    constexpr auto frame(memory::frame frame) -> void
     {
-      m_address = static_cast<std::uint64_t>(address.raw());
+      m_address = static_cast<std::uint64_t>(frame.number());
     }
 
     //! Extract the root paging configuration flags from this value.