diff options
| -rw-r--r-- | arch/x86_64/include/x86_64/cpu/control_register.hpp (renamed from arch/x86_64/include/x86_64/cpu/control_registers.hpp) | 15 | ||||
| -rw-r--r-- | arch/x86_64/include/x86_64/cpu/model_specific_register.hpp | 3 | ||||
| -rw-r--r-- | arch/x86_64/include/x86_64/cpu/registers.hpp | 25 |
3 files changed, 24 insertions, 19 deletions
diff --git a/arch/x86_64/include/x86_64/cpu/control_registers.hpp b/arch/x86_64/include/x86_64/cpu/control_register.hpp index 1f8c690..35ffcae 100644 --- a/arch/x86_64/include/x86_64/cpu/control_registers.hpp +++ b/arch/x86_64/include/x86_64/cpu/control_register.hpp @@ -239,21 +239,6 @@ namespace teachos::cpu::x86_64 static_assert(sizeof(cr3_value) == sizeof(std::uint64_t)); - //! Configuration Register 0. - //! - //! This configuration register holds various control flags to configure the configure the basic operation of the CPU. - using cr0 = control_register<cr0_flags, &impl::cr0_asm>; - - //! Configuration Register 2. - //! - //! This configuration register holds the memory address the access to which has triggered the most recent page fault. - using cr2 = control_register<memory::linear_address, &impl::cr2_asm>; - - //! Configuration Register 3. - //! - //! This register holds the configuration of the virtual memory protection configuration. - using cr3 = control_register<cr3_value, &impl::cr3_asm>; - } // namespace teachos::cpu::x86_64 #endif
\ No newline at end of file diff --git a/arch/x86_64/include/x86_64/cpu/model_specific_register.hpp b/arch/x86_64/include/x86_64/cpu/model_specific_register.hpp index 080b280..857b444 100644 --- a/arch/x86_64/include/x86_64/cpu/model_specific_register.hpp +++ b/arch/x86_64/include/x86_64/cpu/model_specific_register.hpp @@ -143,9 +143,6 @@ namespace teachos::cpu::x86_64 } }; - //! The I32_EFER (Extended Feature Enable Register) MSR - using i32_efer = model_specific_register<ia32_efer_number, ia32_efer_flags>; - } // namespace teachos::cpu::x86_64 #endif
\ No newline at end of file diff --git a/arch/x86_64/include/x86_64/cpu/registers.hpp b/arch/x86_64/include/x86_64/cpu/registers.hpp index cb56270..8eb89e3 100644 --- a/arch/x86_64/include/x86_64/cpu/registers.hpp +++ b/arch/x86_64/include/x86_64/cpu/registers.hpp @@ -1,7 +1,30 @@ #ifndef TEACHOS_X86_64_CPU_REGISTERS_HPP #define TEACHOS_X86_64_CPU_REGISTERS_HPP -#include "x86_64/cpu/control_registers.hpp" // IWYU pragma: export +#include "x86_64/cpu/control_register.hpp" // IWYU pragma: export #include "x86_64/cpu/model_specific_register.hpp" // IWYU pragma: export +namespace teachos::cpu::x86_64 +{ + + //! Configuration Register 0. + //! + //! This configuration register holds various control flags to configure the configure the basic operation of the CPU. + using cr0 = control_register<cr0_flags, &impl::cr0_asm>; + + //! Configuration Register 2. + //! + //! This configuration register holds the memory address the access to which has triggered the most recent page fault. + using cr2 = control_register<memory::linear_address, &impl::cr2_asm>; + + //! Configuration Register 3. + //! + //! This register holds the configuration of the virtual memory protection configuration. + using cr3 = control_register<cr3_value, &impl::cr3_asm>; + + //! The I32_EFER (Extended Feature Enable Register) MSR + using i32_efer = model_specific_register<ia32_efer_number, ia32_efer_flags>; + +} // namespace teachos::cpu::x86_64 + #endif
\ No newline at end of file |