2 files changed, 29 insertions, 15 deletions
diff --git a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp
index 56e0632..83624a9 100644
--- a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp
+++ b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp
@@ -3,6 +3,7 @@
 
 #include "arch/exception_handling/assert.hpp"
 #include "arch/memory/allocator/concept.hpp"
+#include "arch/memory/paging/tlb.hpp"
 #include "arch/memory/paging/virtual_page.hpp"
 
 #include <array>
@@ -10,8 +11,6 @@
 
 namespace teachos::arch::memory::paging
 {
-  std::size_t constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000;
-
   /**
    * @brief Currently active level 4 page table, is used to ensure there is only ever one valid instance and it cannot
    * be copied or constructed again.
@@ -55,18 +54,6 @@ namespace teachos::arch::memory::paging
     auto translate_huge_page(virtual_page page) -> std::optional<allocator::physical_frame>;
 
     /**
-     * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained
-     * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction.
-     *
-     * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for
-     * that page.
-     */
-    static auto invalidate_page_cache(virtual_address address) -> void
-    {
-      asm volatile("invlpg (%0)" ::"r"(address) : "memory");
-    }
-
-    /**
      * @brief Maps a virtual page to a physical frame in the page table with the specified flags.
      *
      * @note Allocates and maps an entry in every page level if it does not exists yet down to level 1. If the level 1
@@ -171,7 +158,8 @@ namespace teachos::arch::memory::paging
           break;
         }
       }
-      invalidate_page_cache(page.start_address());
+
+      tlb_flush(page.start_address());
     }
 
     page_table_handle active_handle;  ///< Underlying active level 4 page table
diff --git a/arch/x86_64/include/arch/memory/paging/tlb.hpp b/arch/x86_64/include/arch/memory/paging/tlb.hpp
new file mode 100644
index 0000000..e74eb74
--- /dev/null
+++ b/arch/x86_64/include/arch/memory/paging/tlb.hpp
@@ -0,0 +1,26 @@
+#ifndef TEACHOS_ARCH_X86_64_MEMORY_PAGING_TLB_HPP
+#define TEACHOS_ARCH_X86_64_MEMORY_PAGING_TLB_HPP
+
+#include "arch/memory/paging/virtual_page.hpp"
+
+namespace teachos::arch::memory::paging
+{
+  std::size_t constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000;
+
+  /**
+   * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained
+   * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction.
+   *
+   * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for
+   * that page.
+   */
+  auto tlb_flush(virtual_address address) -> void;
+
+  /**
+   * @brief Invalidates the translation lookaside buffer (TLB) entry for all page tables
+   */
+  auto tlb_flush_all() -> void;
+
+}  // namespace teachos::arch::memory::paging
+
+#endif
+\ No newline at end of file