diff options
Diffstat (limited to 'arch/x86_64')
5 files changed, 17 insertions, 9 deletions
diff --git a/arch/x86_64/include/arch/memory/cpu/tlb.hpp b/arch/x86_64/include/arch/memory/cpu/tlb.hpp index dc7ec61..21f09e5 100644 --- a/arch/x86_64/include/arch/memory/cpu/tlb.hpp +++ b/arch/x86_64/include/arch/memory/cpu/tlb.hpp @@ -5,8 +5,6 @@ namespace teachos::arch::memory::cpu { - paging::virtual_address constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000; - /** * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction. diff --git a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp index 09fbc76..567a806 100644 --- a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp +++ b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp @@ -164,8 +164,10 @@ namespace teachos::arch::memory::paging break; } } - - cpu::tlb_flush(page.start_address()); + // TODO: Flushing only specifc page does not work and cause temporary_page.map_table_frame to return an invalid + // page table (Memory inside buffer shows nothing) + // cpu::tlb_flush(page.start_address()); + cpu::tlb_flush_all(); } private: diff --git a/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp b/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp index 0786ec1..c91c5f0 100644 --- a/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp +++ b/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp @@ -76,8 +76,6 @@ namespace teachos::arch::memory::paging auto const backup = allocator::physical_frame::containing_address(cpu::read_cr3_register()); auto page_table_level4 = temporary_page.map_table_frame(backup, active_table); - // TODO: Page Table Level 4 is invalid, all entries point to non-existent memory :( - active_table[511].set_entry(inactive_table.page_table_level_4_frame, entry::PRESENT | entry::WRITABLE); cpu::tlb_flush_all(); map_elf_kernel_sections(active_table); diff --git a/arch/x86_64/src/memory/cpu/tlb.cpp b/arch/x86_64/src/memory/cpu/tlb.cpp index bac46b7..1663e80 100644 --- a/arch/x86_64/src/memory/cpu/tlb.cpp +++ b/arch/x86_64/src/memory/cpu/tlb.cpp @@ -1,8 +1,13 @@ #include "arch/memory/cpu/tlb.hpp" +#include "arch/memory/cpu/cr3.hpp" + namespace teachos::arch::memory::cpu { - auto tlb_flush(paging::virtual_address address) -> void { asm volatile("invlpg (%0)" ::"r"(address) : "memory"); } + auto tlb_flush(paging::virtual_address address) -> void + { + asm volatile("invlpg (%[input])" : /* no output from call */ : [input] "r"(address) : "memory"); + } - auto tlb_flush_all() -> void { tlb_flush(PAGE_TABLE_LEVEL_4_ADDRESS); } + auto tlb_flush_all() -> void { write_cr3_register(read_cr3_register()); } } // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/paging/active_page_table.cpp b/arch/x86_64/src/memory/paging/active_page_table.cpp index 3f62419..0113869 100644 --- a/arch/x86_64/src/memory/paging/active_page_table.cpp +++ b/arch/x86_64/src/memory/paging/active_page_table.cpp @@ -2,9 +2,14 @@ namespace teachos::arch::memory::paging { + namespace + { + paging::virtual_address constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000; + } + auto active_page_table::create_or_get() -> active_page_table & { - static page_table_handle active_handle{reinterpret_cast<page_table *>(cpu::PAGE_TABLE_LEVEL_4_ADDRESS), + static page_table_handle active_handle{reinterpret_cast<page_table *>(PAGE_TABLE_LEVEL_4_ADDRESS), page_table_handle::LEVEL4}; static active_page_table active_page{active_handle}; return active_page; |