From 3c01f820a064f3120a46aa3afdd9f88ce9e00db3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Mon, 17 Mar 2025 14:51:24 +0000 Subject: Debug and adjust load task register assembly call. WIP --- arch/x86_64/src/kernel/cpu/tr.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/x86_64/src/kernel/cpu/tr.cpp') diff --git a/arch/x86_64/src/kernel/cpu/tr.cpp b/arch/x86_64/src/kernel/cpu/tr.cpp index d0e037f..e281189 100644 --- a/arch/x86_64/src/kernel/cpu/tr.cpp +++ b/arch/x86_64/src/kernel/cpu/tr.cpp @@ -11,6 +11,12 @@ namespace teachos::arch::kernel::cpu auto load_task_register(uint16_t gdt_offset) -> void { - asm volatile("ltr %[input]" : /* no output from call */ : [input] "r"(gdt_offset)); + // asm volatile("ltr %[input]" : /* no output from call */ : [input] "R"(gdt_offset)); + // https://www.scs.stanford.edu/05au-cs240c/lab/i386/s07_03.htm + asm volatile("mov %[input], %%ax\n" + "ltr %%ax\n" + : /* no output from call */ + : [input] "r"(gdt_offset) + : "ax"); } } // namespace teachos::arch::kernel::cpu -- cgit v1.2.3