From 1275612382c5c9d31ed7b24a2c6d699c14a10081 Mon Sep 17 00:00:00 2001 From: Fabian Imhof Date: Sun, 10 Nov 2024 10:59:22 +0000 Subject: implement model specific register calls --- arch/x86_64/src/memory/cpu/msr.cpp | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/x86_64/src/memory/cpu/msr.cpp (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp new file mode 100644 index 0000000..3a917c9 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/msr.cpp @@ -0,0 +1,29 @@ +#include "arch/memory/cpu/msr.hpp" + +namespace teachos::arch::memory::cpu +{ + uint64_t read_msr(uint32_t msr) + { + uint32_t low, high; + asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(msr)); + return (static_cast(high) << 32) | low; + } + + void write_msr(uint32_t msr, uint64_t value) + { + uint32_t low = value & 0xFFFFFFFF; + uint32_t high = value >> 32; + asm volatile("wrmsr" + : /* no output from call */ + : "c"(msr), "a"(low), "d"(high)); + } + + void set_msr_bit(msr_flags flag) + { + uint64_t efer = read_msr(IA32_EFER); + write_msr(IA32_EFER, static_cast(flag) | efer); + } + + void enable_nxe_bit() { set_msr_bit(msr_flags::NXE); } + +} // namespace teachos::arch::memory::cpu -- cgit v1.2.3