From dc80a11864444cae275e9e7be9ae120a92433034 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Tue, 5 Nov 2024 09:58:05 +0000 Subject: Move tlb into seperate subfolder and create cr3 header for reading and writing. --- arch/x86_64/src/memory/cpu/cr3.cpp | 23 +++++++++++++++++++++++ arch/x86_64/src/memory/cpu/tlb.cpp | 8 ++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/x86_64/src/memory/cpu/cr3.cpp create mode 100644 arch/x86_64/src/memory/cpu/tlb.cpp (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/cr3.cpp b/arch/x86_64/src/memory/cpu/cr3.cpp new file mode 100644 index 0000000..7e48d40 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/cr3.cpp @@ -0,0 +1,23 @@ +#include "arch/memory/cpu/cr3.hpp" + +#include "arch/exception_handling/assert.hpp" + +namespace teachos::arch::memory::cpu +{ + auto read_cr3_register() -> allocator::physical_address + { + allocator::physical_address cr3; + asm volatile("movq %%cr3, %[output]" : [output] "=r"(cr3) : /* no input into call */ : "memory"); + return cr3; + } + + auto write_cr3_register(allocator::physical_address new_p4_table_address) -> void + { + exception_handling::assert(new_p4_table_address % allocator::PAGE_FRAME_SIZE == 0U, + "[CR3] Physical address to be written into register must be page aligned"); + asm volatile("movq %[input], %%cr3" + : /* no output from call */ + : [input] "r"(new_p4_table_address) + : "memory"); + } +} // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/cpu/tlb.cpp b/arch/x86_64/src/memory/cpu/tlb.cpp new file mode 100644 index 0000000..bac46b7 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/tlb.cpp @@ -0,0 +1,8 @@ +#include "arch/memory/cpu/tlb.hpp" + +namespace teachos::arch::memory::cpu +{ + auto tlb_flush(paging::virtual_address address) -> void { asm volatile("invlpg (%0)" ::"r"(address) : "memory"); } + + auto tlb_flush_all() -> void { tlb_flush(PAGE_TABLE_LEVEL_4_ADDRESS); } +} // namespace teachos::arch::memory::cpu -- cgit v1.2.3 From 4c030cbaee174a9f7f42d4f5ca7ddf6debbbe048 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Sat, 9 Nov 2024 16:25:11 +0000 Subject: Fix flush all method and move crash. --- arch/x86_64/src/memory/cpu/tlb.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/tlb.cpp b/arch/x86_64/src/memory/cpu/tlb.cpp index bac46b7..1663e80 100644 --- a/arch/x86_64/src/memory/cpu/tlb.cpp +++ b/arch/x86_64/src/memory/cpu/tlb.cpp @@ -1,8 +1,13 @@ #include "arch/memory/cpu/tlb.hpp" +#include "arch/memory/cpu/cr3.hpp" + namespace teachos::arch::memory::cpu { - auto tlb_flush(paging::virtual_address address) -> void { asm volatile("invlpg (%0)" ::"r"(address) : "memory"); } + auto tlb_flush(paging::virtual_address address) -> void + { + asm volatile("invlpg (%[input])" : /* no output from call */ : [input] "r"(address) : "memory"); + } - auto tlb_flush_all() -> void { tlb_flush(PAGE_TABLE_LEVEL_4_ADDRESS); } + auto tlb_flush_all() -> void { write_cr3_register(read_cr3_register()); } } // namespace teachos::arch::memory::cpu -- cgit v1.2.3 From 1275612382c5c9d31ed7b24a2c6d699c14a10081 Mon Sep 17 00:00:00 2001 From: Fabian Imhof Date: Sun, 10 Nov 2024 10:59:22 +0000 Subject: implement model specific register calls --- arch/x86_64/src/memory/cpu/msr.cpp | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/x86_64/src/memory/cpu/msr.cpp (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp new file mode 100644 index 0000000..3a917c9 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/msr.cpp @@ -0,0 +1,29 @@ +#include "arch/memory/cpu/msr.hpp" + +namespace teachos::arch::memory::cpu +{ + uint64_t read_msr(uint32_t msr) + { + uint32_t low, high; + asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(msr)); + return (static_cast(high) << 32) | low; + } + + void write_msr(uint32_t msr, uint64_t value) + { + uint32_t low = value & 0xFFFFFFFF; + uint32_t high = value >> 32; + asm volatile("wrmsr" + : /* no output from call */ + : "c"(msr), "a"(low), "d"(high)); + } + + void set_msr_bit(msr_flags flag) + { + uint64_t efer = read_msr(IA32_EFER); + write_msr(IA32_EFER, static_cast(flag) | efer); + } + + void enable_nxe_bit() { set_msr_bit(msr_flags::NXE); } + +} // namespace teachos::arch::memory::cpu -- cgit v1.2.3 From 45e7b24f19b3c4557f98996a44d8857d750ca5b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Sun, 10 Nov 2024 11:45:26 +0000 Subject: Adjust comments and constant --- arch/x86_64/src/memory/cpu/control_register.cpp | 66 +++++++++++++++++++++++++ arch/x86_64/src/memory/cpu/cr3.cpp | 23 --------- arch/x86_64/src/memory/cpu/msr.cpp | 18 ++++--- arch/x86_64/src/memory/cpu/tlb.cpp | 7 ++- 4 files changed, 82 insertions(+), 32 deletions(-) create mode 100644 arch/x86_64/src/memory/cpu/control_register.cpp delete mode 100644 arch/x86_64/src/memory/cpu/cr3.cpp (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/control_register.cpp b/arch/x86_64/src/memory/cpu/control_register.cpp new file mode 100644 index 0000000..38a887c --- /dev/null +++ b/arch/x86_64/src/memory/cpu/control_register.cpp @@ -0,0 +1,66 @@ +#include "arch/memory/cpu/control_register.hpp" + +#include "arch/exception_handling/assert.hpp" + +namespace teachos::arch::memory::cpu +{ + auto read_control_register(control_register cr) -> std::size_t + { + std::size_t current_value; + switch (cr) + { + case control_register::CR0: + asm volatile("movq %%cr0, %[output]" : [output] "=r"(current_value)); + break; + case control_register::CR2: + asm volatile("movq %%cr2, %[output]" : [output] "=r"(current_value)); + break; + case control_register::CR3: + asm volatile("movq %%cr3, %[output]" : [output] "=r"(current_value)); + break; + case control_register::CR4: + asm volatile("movq %%cr4, %[output]" : [output] "=r"(current_value)); + break; + default: + exception_handling::assert(false, + "[Control Register] Attempted to read non-existent or reserved control register"); + break; + } + return current_value; + } + + auto write_control_register(control_register cr, std::size_t new_value) -> void + { + switch (cr) + { + case control_register::CR0: + asm volatile("movq %[input], %%cr0" + : /* no output from call */ + : [input] "r"(new_value) + : "memory"); + break; + case control_register::CR2: + asm volatile("movq %[input], %%cr2" + : /* no output from call */ + : [input] "r"(new_value) + : "memory"); + break; + case control_register::CR3: + asm volatile("movq %[input], %%cr3" + : /* no output from call */ + : [input] "r"(new_value) + : "memory"); + break; + case control_register::CR4: + asm volatile("movq %[input], %%cr4" + : /* no output from call */ + : [input] "r"(new_value) + : "memory"); + break; + default: + exception_handling::assert(false, + "[Control Register] Attempted to write non-existent or reserved control register"); + break; + } + } +} // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/cpu/cr3.cpp b/arch/x86_64/src/memory/cpu/cr3.cpp deleted file mode 100644 index 7e48d40..0000000 --- a/arch/x86_64/src/memory/cpu/cr3.cpp +++ /dev/null @@ -1,23 +0,0 @@ -#include "arch/memory/cpu/cr3.hpp" - -#include "arch/exception_handling/assert.hpp" - -namespace teachos::arch::memory::cpu -{ - auto read_cr3_register() -> allocator::physical_address - { - allocator::physical_address cr3; - asm volatile("movq %%cr3, %[output]" : [output] "=r"(cr3) : /* no input into call */ : "memory"); - return cr3; - } - - auto write_cr3_register(allocator::physical_address new_p4_table_address) -> void - { - exception_handling::assert(new_p4_table_address % allocator::PAGE_FRAME_SIZE == 0U, - "[CR3] Physical address to be written into register must be page aligned"); - asm volatile("movq %[input], %%cr3" - : /* no output from call */ - : [input] "r"(new_p4_table_address) - : "memory"); - } -} // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp index 3a917c9..6e3d1d3 100644 --- a/arch/x86_64/src/memory/cpu/msr.cpp +++ b/arch/x86_64/src/memory/cpu/msr.cpp @@ -2,14 +2,19 @@ namespace teachos::arch::memory::cpu { - uint64_t read_msr(uint32_t msr) + namespace + { + constexpr uint32_t IA32_EFER_ADDRESS = 0xC0000080; + } + + auto read_msr(uint32_t msr) -> uint64_t { uint32_t low, high; asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(msr)); return (static_cast(high) << 32) | low; } - void write_msr(uint32_t msr, uint64_t value) + auto write_msr(uint32_t msr, uint64_t value) -> void { uint32_t low = value & 0xFFFFFFFF; uint32_t high = value >> 32; @@ -18,12 +23,11 @@ namespace teachos::arch::memory::cpu : "c"(msr), "a"(low), "d"(high)); } - void set_msr_bit(msr_flags flag) + auto set_efer_bit(efer_flags flag) -> void { - uint64_t efer = read_msr(IA32_EFER); - write_msr(IA32_EFER, static_cast(flag) | efer); + uint64_t const efer = read_msr(IA32_EFER_ADDRESS); + write_msr(IA32_EFER_ADDRESS, static_cast(flag) | efer); } - void enable_nxe_bit() { set_msr_bit(msr_flags::NXE); } - + auto enable_nxe_bit() -> void { set_efer_bit(efer_flags::NXE); } } // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/cpu/tlb.cpp b/arch/x86_64/src/memory/cpu/tlb.cpp index 1663e80..591d9fc 100644 --- a/arch/x86_64/src/memory/cpu/tlb.cpp +++ b/arch/x86_64/src/memory/cpu/tlb.cpp @@ -1,6 +1,6 @@ #include "arch/memory/cpu/tlb.hpp" -#include "arch/memory/cpu/cr3.hpp" +#include "arch/memory/cpu/control_register.hpp" namespace teachos::arch::memory::cpu { @@ -9,5 +9,8 @@ namespace teachos::arch::memory::cpu asm volatile("invlpg (%[input])" : /* no output from call */ : [input] "r"(address) : "memory"); } - auto tlb_flush_all() -> void { write_cr3_register(read_cr3_register()); } + auto tlb_flush_all() -> void + { + write_control_register(cpu::control_register::CR3, read_control_register(cpu::control_register::CR3)); + } } // namespace teachos::arch::memory::cpu -- cgit v1.2.3 From 8eb68ccb8837ba867550d16f967d9ef21921abe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Sun, 10 Nov 2024 12:08:02 +0000 Subject: Finish control register and adjust msr --- arch/x86_64/src/memory/cpu/control_register.cpp | 30 ++++++++++++++++--------- arch/x86_64/src/memory/cpu/msr.cpp | 8 +++---- 2 files changed, 22 insertions(+), 16 deletions(-) (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/control_register.cpp b/arch/x86_64/src/memory/cpu/control_register.cpp index 38a887c..7624244 100644 --- a/arch/x86_64/src/memory/cpu/control_register.cpp +++ b/arch/x86_64/src/memory/cpu/control_register.cpp @@ -2,24 +2,26 @@ #include "arch/exception_handling/assert.hpp" +#include + namespace teachos::arch::memory::cpu { - auto read_control_register(control_register cr) -> std::size_t + auto read_control_register(control_register cr) -> uint64_t { - std::size_t current_value; + uint64_t current_value; switch (cr) { case control_register::CR0: - asm volatile("movq %%cr0, %[output]" : [output] "=r"(current_value)); + asm volatile("mov %%cr0, %[output]" : [output] "=r"(current_value)); break; case control_register::CR2: - asm volatile("movq %%cr2, %[output]" : [output] "=r"(current_value)); + asm volatile("mov %%cr2, %[output]" : [output] "=r"(current_value)); break; case control_register::CR3: - asm volatile("movq %%cr3, %[output]" : [output] "=r"(current_value)); + asm volatile("mov %%cr3, %[output]" : [output] "=r"(current_value)); break; case control_register::CR4: - asm volatile("movq %%cr4, %[output]" : [output] "=r"(current_value)); + asm volatile("mov %%cr4, %[output]" : [output] "=r"(current_value)); break; default: exception_handling::assert(false, @@ -29,30 +31,30 @@ namespace teachos::arch::memory::cpu return current_value; } - auto write_control_register(control_register cr, std::size_t new_value) -> void + auto write_control_register(control_register cr, uint64_t new_value) -> void { switch (cr) { case control_register::CR0: - asm volatile("movq %[input], %%cr0" + asm volatile("mov %[input], %%cr0" : /* no output from call */ : [input] "r"(new_value) : "memory"); break; case control_register::CR2: - asm volatile("movq %[input], %%cr2" + asm volatile("mov %[input], %%cr2" : /* no output from call */ : [input] "r"(new_value) : "memory"); break; case control_register::CR3: - asm volatile("movq %[input], %%cr3" + asm volatile("mov %[input], %%cr3" : /* no output from call */ : [input] "r"(new_value) : "memory"); break; case control_register::CR4: - asm volatile("movq %[input], %%cr4" + asm volatile("mov %[input], %%cr4" : /* no output from call */ : [input] "r"(new_value) : "memory"); @@ -63,4 +65,10 @@ namespace teachos::arch::memory::cpu break; } } + + auto set_cr2_bit(cr2_flags flag) -> void + { + auto const cr2 = read_control_register(control_register::CR2); + write_control_register(control_register::CR2, static_cast::type>(flag) | cr2); + } } // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp index 6e3d1d3..b83f902 100644 --- a/arch/x86_64/src/memory/cpu/msr.cpp +++ b/arch/x86_64/src/memory/cpu/msr.cpp @@ -4,7 +4,7 @@ namespace teachos::arch::memory::cpu { namespace { - constexpr uint32_t IA32_EFER_ADDRESS = 0xC0000080; + auto constexpr IA32_EFER_ADDRESS = 0xC0000080; } auto read_msr(uint32_t msr) -> uint64_t @@ -25,9 +25,7 @@ namespace teachos::arch::memory::cpu auto set_efer_bit(efer_flags flag) -> void { - uint64_t const efer = read_msr(IA32_EFER_ADDRESS); - write_msr(IA32_EFER_ADDRESS, static_cast(flag) | efer); + auto const efer = read_msr(IA32_EFER_ADDRESS); + write_msr(IA32_EFER_ADDRESS, static_cast::type>(flag) | efer); } - - auto enable_nxe_bit() -> void { set_efer_bit(efer_flags::NXE); } } // namespace teachos::arch::memory::cpu -- cgit v1.2.3 From 4ff0477e844fe13620b02c197a8db4c01809399f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Mon, 9 Dec 2024 15:16:50 +0000 Subject: Fix method writing to wrong CR register and improve doxygen comments. --- arch/x86_64/src/memory/cpu/control_register.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/x86_64/src/memory/cpu') diff --git a/arch/x86_64/src/memory/cpu/control_register.cpp b/arch/x86_64/src/memory/cpu/control_register.cpp index 7624244..298874f 100644 --- a/arch/x86_64/src/memory/cpu/control_register.cpp +++ b/arch/x86_64/src/memory/cpu/control_register.cpp @@ -66,9 +66,9 @@ namespace teachos::arch::memory::cpu } } - auto set_cr2_bit(cr2_flags flag) -> void + auto set_cr0_bit(cr0_flags flag) -> void { - auto const cr2 = read_control_register(control_register::CR2); - write_control_register(control_register::CR2, static_cast::type>(flag) | cr2); + auto const cr0 = read_control_register(control_register::CR0); + write_control_register(control_register::CR0, static_cast::type>(flag) | cr0); } } // namespace teachos::arch::memory::cpu -- cgit v1.2.3