From dc80a11864444cae275e9e7be9ae120a92433034 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Tue, 5 Nov 2024 09:58:05 +0000 Subject: Move tlb into seperate subfolder and create cr3 header for reading and writing. --- arch/x86_64/CMakeLists.txt | 3 ++- arch/x86_64/include/arch/boot/pointers.hpp | 2 +- arch/x86_64/include/arch/memory/cpu/cr3.hpp | 27 ++++++++++++++++++++++ arch/x86_64/include/arch/memory/cpu/tlb.hpp | 26 +++++++++++++++++++++ .../arch/memory/paging/active_page_table.hpp | 4 ++-- .../include/arch/memory/paging/kernel_mapper.hpp | 15 +++++++++--- arch/x86_64/include/arch/memory/paging/tlb.hpp | 26 --------------------- arch/x86_64/src/memory/cpu/cr3.cpp | 23 ++++++++++++++++++ arch/x86_64/src/memory/cpu/tlb.cpp | 8 +++++++ .../x86_64/src/memory/paging/active_page_table.cpp | 2 +- arch/x86_64/src/memory/paging/tlb.cpp | 7 ------ 11 files changed, 102 insertions(+), 41 deletions(-) create mode 100644 arch/x86_64/include/arch/memory/cpu/cr3.hpp create mode 100644 arch/x86_64/include/arch/memory/cpu/tlb.hpp delete mode 100644 arch/x86_64/include/arch/memory/paging/tlb.hpp create mode 100644 arch/x86_64/src/memory/cpu/cr3.cpp create mode 100644 arch/x86_64/src/memory/cpu/tlb.cpp delete mode 100644 arch/x86_64/src/memory/paging/tlb.cpp (limited to 'arch') diff --git a/arch/x86_64/CMakeLists.txt b/arch/x86_64/CMakeLists.txt index 42aa6ef..9fa8181 100644 --- a/arch/x86_64/CMakeLists.txt +++ b/arch/x86_64/CMakeLists.txt @@ -52,7 +52,8 @@ target_sources("_memory" PRIVATE "src/memory/paging/virtual_page.cpp" "src/memory/paging/active_page_table.cpp" "src/memory/paging/inactive_page_table.cpp" - "src/memory/paging/tlb.cpp" + "src/memory/cpu/tlb.cpp" + "src/memory/cpu/cr3.cpp" ) #[============================================================================[ diff --git a/arch/x86_64/include/arch/boot/pointers.hpp b/arch/x86_64/include/arch/boot/pointers.hpp index 25800f4..1172443 100644 --- a/arch/x86_64/include/arch/boot/pointers.hpp +++ b/arch/x86_64/include/arch/boot/pointers.hpp @@ -8,4 +8,4 @@ namespace teachos::arch::boot extern "C" size_t const multiboot_information_pointer; } // namespace teachos::arch::boot -#endif +#endif // TEACHOS_ARCH_X86_64_BOOT_POINTERS_HPP diff --git a/arch/x86_64/include/arch/memory/cpu/cr3.hpp b/arch/x86_64/include/arch/memory/cpu/cr3.hpp new file mode 100644 index 0000000..51d5055 --- /dev/null +++ b/arch/x86_64/include/arch/memory/cpu/cr3.hpp @@ -0,0 +1,27 @@ +#ifndef TEACHOS_ARCH_X86_64_MEMORY_CPU_CR3_HPP +#define TEACHOS_ARCH_X86_64_MEMORY_CPU_CR3_HPP + +#include "arch/memory/allocator/physical_frame.hpp" + +namespace teachos::arch::memory::cpu +{ + /** + * @brief Reads the value of the cr3 register. + * + * @note The cr3 register value represents the physical address of the level 4 page table used for paging in the + * system. Therefore reading this value allows to access the level 4 page table directly. Instead of over the virtual + * address 0xffffffff'fffff000, which then has to be first translated into a physical address. + * + * @return Physical address the level 4 page table is located at. + */ + auto read_cr3_register() -> allocator::physical_address; + + /** + * @brief Writes the given value into the cr3 register. + * + * @param new_p4_table_address Physical address the newly kernel mapped level 4 page table is located at. + */ + auto write_cr3_register(allocator::physical_address new_p4_table_address) -> void; +} // namespace teachos::arch::memory::cpu + +#endif // TEACHOS_ARCH_X86_64_MEMORY_CPU_CR3_HPP diff --git a/arch/x86_64/include/arch/memory/cpu/tlb.hpp b/arch/x86_64/include/arch/memory/cpu/tlb.hpp new file mode 100644 index 0000000..dc7ec61 --- /dev/null +++ b/arch/x86_64/include/arch/memory/cpu/tlb.hpp @@ -0,0 +1,26 @@ +#ifndef TEACHOS_ARCH_X86_64_MEMORY_CPU_TLB_HPP +#define TEACHOS_ARCH_X86_64_MEMORY_CPU_TLB_HPP + +#include "arch/memory/paging/virtual_page.hpp" + +namespace teachos::arch::memory::cpu +{ + paging::virtual_address constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000; + + /** + * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained + * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction. + * + * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for + * that page. + */ + auto tlb_flush(paging::virtual_address address) -> void; + + /** + * @brief Invalidates the translation lookaside buffer (TLB) entry for all page tables + */ + auto tlb_flush_all() -> void; + +} // namespace teachos::arch::memory::cpu + +#endif // TEACHOS_ARCH_X86_64_MEMORY_CPU_TLB_HPP diff --git a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp index 0561420..09fbc76 100644 --- a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp +++ b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp @@ -3,7 +3,7 @@ #include "arch/exception_handling/assert.hpp" #include "arch/memory/allocator/concept.hpp" -#include "arch/memory/paging/tlb.hpp" +#include "arch/memory/cpu/tlb.hpp" #include "arch/memory/paging/virtual_page.hpp" #include @@ -165,7 +165,7 @@ namespace teachos::arch::memory::paging } } - tlb_flush(page.start_address()); + cpu::tlb_flush(page.start_address()); } private: diff --git a/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp b/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp index 23a18dd..9803050 100644 --- a/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp +++ b/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp @@ -1,6 +1,7 @@ #ifndef TEACHOS_ARCH_X86_64_MEMORY_PAGING_KERNEL_MAPPER_HPP #define TEACHOS_ARCH_X86_64_MEMORY_PAGING_KERNEL_MAPPER_HPP +#include "arch/memory/cpu/cr3.hpp" #include "arch/memory/paging/active_page_table.hpp" #include "arch/memory/paging/inactive_page_table.hpp" #include "arch/memory/paging/temporary_page.hpp" @@ -68,21 +69,29 @@ namespace teachos::arch::memory::paging auto remap_elf_kernel_sections(inactive_page_table inactive_table, temporary_page & temporary_page, active_page_table & active_table) -> void { - auto const physical_address = active_table.translate_address(PAGE_TABLE_LEVEL_4_ADDRESS); + auto const physical_address = active_table.translate_address(cpu::PAGE_TABLE_LEVEL_4_ADDRESS); exception_handling::assert(physical_address.has_value(), "[Kernel Mapper] Physical address for active table not mapped"); auto const backup = allocator::physical_frame::containing_address(physical_address.value()); + auto const backup2 = allocator::physical_frame::containing_address(cpu::read_cr3_register()); + cpu::write_cr3_register(0x221000); + auto const backup3 = cpu::read_cr3_register(); + + if (backup == backup2 && backup3 == 0x221000) + { + } + auto page_table_level4 = temporary_page.map_table_frame(backup, active_table); // TODO: Page Table Level 4 is invalid, all entries point to non-existent memory :( active_table[511].set_entry(inactive_table.page_table_level_4_frame, entry::PRESENT | entry::WRITABLE); - tlb_flush_all(); + cpu::tlb_flush_all(); map_elf_kernel_sections(active_table); page_table_level4[511].set_entry(backup, entry::PRESENT | entry::WRITABLE); - tlb_flush_all(); + cpu::tlb_flush_all(); temporary_page.unmap_page(active_table); } diff --git a/arch/x86_64/include/arch/memory/paging/tlb.hpp b/arch/x86_64/include/arch/memory/paging/tlb.hpp deleted file mode 100644 index 85c4152..0000000 --- a/arch/x86_64/include/arch/memory/paging/tlb.hpp +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef TEACHOS_ARCH_X86_64_MEMORY_PAGING_TLB_HPP -#define TEACHOS_ARCH_X86_64_MEMORY_PAGING_TLB_HPP - -#include "arch/memory/paging/virtual_page.hpp" - -namespace teachos::arch::memory::paging -{ - virtual_address constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000; - - /** - * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained - * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction. - * - * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for - * that page. - */ - auto tlb_flush(virtual_address address) -> void; - - /** - * @brief Invalidates the translation lookaside buffer (TLB) entry for all page tables - */ - auto tlb_flush_all() -> void; - -} // namespace teachos::arch::memory::paging - -#endif // TEACHOS_ARCH_X86_64_MEMORY_PAGING_TLB_HPP diff --git a/arch/x86_64/src/memory/cpu/cr3.cpp b/arch/x86_64/src/memory/cpu/cr3.cpp new file mode 100644 index 0000000..7e48d40 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/cr3.cpp @@ -0,0 +1,23 @@ +#include "arch/memory/cpu/cr3.hpp" + +#include "arch/exception_handling/assert.hpp" + +namespace teachos::arch::memory::cpu +{ + auto read_cr3_register() -> allocator::physical_address + { + allocator::physical_address cr3; + asm volatile("movq %%cr3, %[output]" : [output] "=r"(cr3) : /* no input into call */ : "memory"); + return cr3; + } + + auto write_cr3_register(allocator::physical_address new_p4_table_address) -> void + { + exception_handling::assert(new_p4_table_address % allocator::PAGE_FRAME_SIZE == 0U, + "[CR3] Physical address to be written into register must be page aligned"); + asm volatile("movq %[input], %%cr3" + : /* no output from call */ + : [input] "r"(new_p4_table_address) + : "memory"); + } +} // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/cpu/tlb.cpp b/arch/x86_64/src/memory/cpu/tlb.cpp new file mode 100644 index 0000000..bac46b7 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/tlb.cpp @@ -0,0 +1,8 @@ +#include "arch/memory/cpu/tlb.hpp" + +namespace teachos::arch::memory::cpu +{ + auto tlb_flush(paging::virtual_address address) -> void { asm volatile("invlpg (%0)" ::"r"(address) : "memory"); } + + auto tlb_flush_all() -> void { tlb_flush(PAGE_TABLE_LEVEL_4_ADDRESS); } +} // namespace teachos::arch::memory::cpu diff --git a/arch/x86_64/src/memory/paging/active_page_table.cpp b/arch/x86_64/src/memory/paging/active_page_table.cpp index 033a363..3f62419 100644 --- a/arch/x86_64/src/memory/paging/active_page_table.cpp +++ b/arch/x86_64/src/memory/paging/active_page_table.cpp @@ -4,7 +4,7 @@ namespace teachos::arch::memory::paging { auto active_page_table::create_or_get() -> active_page_table & { - static page_table_handle active_handle{reinterpret_cast(PAGE_TABLE_LEVEL_4_ADDRESS), + static page_table_handle active_handle{reinterpret_cast(cpu::PAGE_TABLE_LEVEL_4_ADDRESS), page_table_handle::LEVEL4}; static active_page_table active_page{active_handle}; return active_page; diff --git a/arch/x86_64/src/memory/paging/tlb.cpp b/arch/x86_64/src/memory/paging/tlb.cpp deleted file mode 100644 index c1160dc..0000000 --- a/arch/x86_64/src/memory/paging/tlb.cpp +++ /dev/null @@ -1,7 +0,0 @@ -#include "arch/memory/paging/tlb.hpp" - -namespace teachos::arch::memory::paging -{ - auto tlb_flush(virtual_address address) -> void { asm volatile("invlpg (%0)" ::"r"(address) : "memory"); } - auto tlb_flush_all() -> void { tlb_flush(PAGE_TABLE_LEVEL_4_ADDRESS); } -} // namespace teachos::arch::memory::paging -- cgit v1.2.3