From 82bd19117313e6d61ab2ac03583e22b8a627f14a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matteo=20Gm=C3=BCr?= Date: Wed, 4 Dec 2024 15:32:19 +0000 Subject: Add doxygen docs file --- docs/arch/x86_64/memory/cpu/control_register.rst | 5 +++++ docs/arch/x86_64/memory/cpu/msr.rst | 5 +++++ docs/arch/x86_64/memory/cpu/tlb.rst | 5 +++++ 3 files changed, 15 insertions(+) create mode 100644 docs/arch/x86_64/memory/cpu/control_register.rst create mode 100644 docs/arch/x86_64/memory/cpu/msr.rst create mode 100644 docs/arch/x86_64/memory/cpu/tlb.rst (limited to 'docs/arch/x86_64/memory/cpu') diff --git a/docs/arch/x86_64/memory/cpu/control_register.rst b/docs/arch/x86_64/memory/cpu/control_register.rst new file mode 100644 index 0000000..f087112 --- /dev/null +++ b/docs/arch/x86_64/memory/cpu/control_register.rst @@ -0,0 +1,5 @@ +CPU Control Registers +======================= + +.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/control_register.hpp + diff --git a/docs/arch/x86_64/memory/cpu/msr.rst b/docs/arch/x86_64/memory/cpu/msr.rst new file mode 100644 index 0000000..c67d51c --- /dev/null +++ b/docs/arch/x86_64/memory/cpu/msr.rst @@ -0,0 +1,5 @@ +CPU Model-Specific Register +======================= + +.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/msr.hpp + diff --git a/docs/arch/x86_64/memory/cpu/tlb.rst b/docs/arch/x86_64/memory/cpu/tlb.rst new file mode 100644 index 0000000..0d482dc --- /dev/null +++ b/docs/arch/x86_64/memory/cpu/tlb.rst @@ -0,0 +1,5 @@ +CPU Translation Lookaside Buffer +======================= + +.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/tlb.hpp + -- cgit v1.2.3