x86_64: clean up hw details

7 files changed, 51 insertions, 62 deletions

diff --git a/arch/x86_64/CMakeLists.txt b/arch/x86_64/CMakeLists.txt
index ddc2d46..c585cbf 100644
--- a/arch/x86_64/CMakeLists.txt
+++ b/arch/x86_64/CMakeLists.txt
@@ -22,7 +22,11 @@ target_sources("x86_64" PRIVATE
     "src/boot/initialize_runtime.cpp"
     "src/boot/multiboot.s"
 
+    # CPU intrinsics
+    "src/cpu/registers.cpp"
+
     # Memory management
+    "src/memory/mmu.cpp"
     "src/memory/region_allocator.cpp"
 
     # VGA text mode
diff --git a/arch/x86_64/include/arch/boot/pointers.hpp b/arch/x86_64/include/arch/boot/pointers.hpp
deleted file mode 100644
index fe9c657..0000000
--- a/arch/x86_64/include/arch/boot/pointers.hpp
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef TEACHOS_ARCH_X86_64_BOOT_POINTERS_HPP
-#define TEACHOS_ARCH_X86_64_BOOT_POINTERS_HPP
-
-#include <cstddef>
-
-namespace teachos::arch::boot
-{
-  /**
-   * @brief Address pointing to the start of the multiboot information structure.
-   */
-  extern "C" size_t const multiboot_information_pointer;
-
-}  // namespace teachos::arch::boot
-
-#endif  // TEACHOS_ARCH_X86_64_BOOT_POINTERS_HPP
diff --git a/arch/x86_64/include/arch/kernel/cpu/control_register.hpp b/arch/x86_64/include/x86_64/cpu/registers.hpp
index dcaf02d..607d559 100644
--- a/arch/x86_64/include/arch/kernel/cpu/control_register.hpp
+++ b/arch/x86_64/include/x86_64/cpu/registers.hpp
@@ -1,10 +1,11 @@
-#ifndef TEACHOS_ARCH_X86_64_KERNEL_CPU_CR3_HPP
-#define TEACHOS_ARCH_X86_64_KERNEL_CPU_CR3_HPP
+#ifndef TEACHOS_X86_64_CPU_REGISTERS_HPP
+#define TEACHOS_X86_64_CPU_REGISTERS_HPP
 
 #include <cstdint>
 
-namespace teachos::arch::kernel::cpu
+namespace teachos::x86_64::cpu
 {
+
   /**
    * @brief Control registers that can be read and written to.
    *
@@ -14,16 +15,16 @@ namespace teachos::arch::kernel::cpu
    */
   enum struct control_register : uint8_t
   {
-    CR0,  ///< Contains various control flags that modify basic operation of the processor, Machine Status World (MSW)
+    cr0,  ///< Contains various control flags that modify basic operation of the processor, Machine Status World (MSW)
           ///< register.
-    CR2 = 2U,  ///< Contains Page Fault Linear Address (PFLA), when page fault occurs address program attended to accces
+    cr2 = 2U,  ///< Contains Page Fault Linear Address (PFLA), when page fault occurs address program attended to accces
                ///< is stored here.
-    CR3,  ///< Enables process to translate linear addresses into physical addresses using paging, CR0 bit 32 Paging
+    cr3,  ///< Enables process to translate linear addresses into physical addresses using paging, CR0 bit 32 Paging
           ///< (PG) needs to be enabled simply contains the register value that represents the physical address of the
           ///< level 4 page table used for paging in the system. Therefore reading this value allows to access the level
           ///< 4 page table directly. Instead of over the virtual address 0xffffffff'fffff000, which then has to be
           ///< first translated into a physical address.
-    CR4   ///< Used in protected mode to control operations.
+    cr4   ///< Used in protected mode to control operations.
   };
 
   /**
@@ -66,6 +67,6 @@ namespace teachos::arch::kernel::cpu
    */
   auto set_cr0_bit(cr0_flags flag) -> void;
 
-}  // namespace teachos::arch::kernel::cpu
+}  // namespace teachos::x86_64::cpu
 
-#endif  // TEACHOS_ARCH_X86_64_KERNEL_CPU_CR3_HPP
+#endif
\ No newline at end of file
diff --git a/arch/x86_64/include/arch/kernel/cpu/tlb.hpp b/arch/x86_64/include/x86_64/memory/mmu.hpp
index f3e58a6..b03ffa2 100644
--- a/arch/x86_64/include/arch/kernel/cpu/tlb.hpp
+++ b/arch/x86_64/include/x86_64/memory/mmu.hpp
@@ -1,9 +1,9 @@
-#ifndef TEACHOS_ARCH_X86_64_KERNEL_CPU_TLB_HPP
-#define TEACHOS_ARCH_X86_64_KERNEL_CPU_TLB_HPP
+#ifndef TEACHOS_X86_64_MEMORY_MMU_HPP
+#define TEACHOS_X86_64_MEMORY_MMU_HPP
 
-#include "arch/memory/paging/virtual_page.hpp"
+#include "x86_64/memory/address.hpp"
 
-namespace teachos::arch::kernel::cpu
+namespace teachos::x86_64::memory
 {
   /**
    * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained
@@ -12,7 +12,7 @@ namespace teachos::arch::kernel::cpu
    * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for
    * that page.
    */
-  auto tlb_flush(memory::paging::virtual_address address) -> void;
+  auto tlb_flush(linear_address address) -> void;
 
   /**
    * @brief Invalidates the translation lookaside buffer (TLB) entry for all page tables.
@@ -22,6 +22,6 @@ namespace teachos::arch::kernel::cpu
    */
   auto tlb_flush_all() -> void;
 
-}  // namespace teachos::arch::kernel::cpu
+}  // namespace teachos::x86_64::memory
 
-#endif  // TEACHOS_ARCH_X86_64_KERNEL_CPU_TLB_HPP
+#endif
\ No newline at end of file
diff --git a/arch/x86_64/src/kernel/cpu/control_register.cpp b/arch/x86_64/src/cpu/registers.cpp
index 41b8cd7..7ade98d 100644
--- a/arch/x86_64/src/kernel/cpu/control_register.cpp
+++ b/arch/x86_64/src/cpu/registers.cpp
@@ -1,26 +1,24 @@
-#include "arch/kernel/cpu/control_register.hpp"
-
-#include "arch/exception_handling/panic.hpp"
+#include "x86_64/cpu/registers.hpp"
 
 #include <type_traits>
 
-namespace teachos::arch::kernel::cpu
+namespace teachos::x86_64::cpu
 {
   auto read_control_register(control_register cr) -> uint64_t
   {
     uint64_t current_value;
     switch (cr)
     {
-      case control_register::CR0:
+      case control_register::cr0:
         asm volatile("mov %%cr0, %[output]" : [output] "=r"(current_value));
         break;
-      case control_register::CR2:
+      case control_register::cr2:
         asm volatile("mov %%cr2, %[output]" : [output] "=r"(current_value));
         break;
-      case control_register::CR3:
+      case control_register::cr3:
         asm volatile("mov %%cr3, %[output]" : [output] "=r"(current_value));
         break;
-      case control_register::CR4:
+      case control_register::cr4:
         asm volatile("mov %%cr4, %[output]" : [output] "=r"(current_value));
         break;
     }
@@ -31,25 +29,25 @@ namespace teachos::arch::kernel::cpu
   {
     switch (cr)
     {
-      case control_register::CR0:
+      case control_register::cr0:
         asm volatile("mov %[input], %%cr0"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
         break;
-      case control_register::CR2:
+      case control_register::cr2:
         asm volatile("mov %[input], %%cr2"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
         break;
-      case control_register::CR3:
+      case control_register::cr3:
         asm volatile("mov %[input], %%cr3"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
         break;
-      case control_register::CR4:
+      case control_register::cr4:
         asm volatile("mov %[input], %%cr4"
                      : /* no output from call */
                      : [input] "r"(new_value)
@@ -60,7 +58,7 @@ namespace teachos::arch::kernel::cpu
 
   auto set_cr0_bit(cr0_flags flag) -> void
   {
-    auto const cr0 = read_control_register(control_register::CR0);
-    write_control_register(control_register::CR0, static_cast<std::underlying_type<cr0_flags>::type>(flag) | cr0);
+    auto const cr0 = read_control_register(control_register::cr0);
+    write_control_register(control_register::cr0, static_cast<std::underlying_type<cr0_flags>::type>(flag) | cr0);
   }
-}  // namespace teachos::arch::kernel::cpu
+}  // namespace teachos::x86_64::cpu
diff --git a/arch/x86_64/src/kernel/cpu/tlb.cpp b/arch/x86_64/src/kernel/cpu/tlb.cpp
deleted file mode 100644
index a09001c..0000000
--- a/arch/x86_64/src/kernel/cpu/tlb.cpp
+++ /dev/null
@@ -1,16 +0,0 @@
-#include "arch/kernel/cpu/tlb.hpp"
-
-#include "arch/kernel/cpu/control_register.hpp"
-
-namespace teachos::arch::kernel::cpu
-{
-  auto tlb_flush(memory::paging::virtual_address address) -> void
-  {
-    asm volatile("invlpg (%[input])" : /* no output from call */ : [input] "r"(address) : "memory");
-  }
-
-  auto tlb_flush_all() -> void
-  {
-    write_control_register(cpu::control_register::CR3, read_control_register(cpu::control_register::CR3));
-  }
-}  // namespace teachos::arch::kernel::cpu
diff --git a/arch/x86_64/src/memory/mmu.cpp b/arch/x86_64/src/memory/mmu.cpp
new file mode 100644
index 0000000..31783fe
--- /dev/null
+++ b/arch/x86_64/src/memory/mmu.cpp
@@ -0,0 +1,17 @@
+#include "x86_64/memory/mmu.hpp"
+
+#include "x86_64/cpu/registers.hpp"
+
+namespace teachos::x86_64::memory
+{
+  auto tlb_flush(linear_address address) -> void
+  {
+    asm volatile("invlpg (%[input])" : /* no output from call */ : [input] "r"(address) : "memory");
+  }
+
+  auto tlb_flush_all() -> void
+  {
+    auto current_value = cpu::read_control_register(cpu::control_register::cr3);
+    cpu::write_control_register(cpu::control_register::cr3, current_value);
+  }
+}  // namespace teachos::x86_64::memory