Fix method writing to wrong CR register and improve doxygen comments.

10 files changed, 39 insertions, 33 deletions

diff --git a/arch/x86_64/include/arch/exception_handling/assert.hpp b/arch/x86_64/include/arch/exception_handling/assert.hpp
index 7dc4381..1286768 100644
--- a/arch/x86_64/include/arch/exception_handling/assert.hpp
+++ b/arch/x86_64/include/arch/exception_handling/assert.hpp
@@ -5,7 +5,7 @@ namespace teachos::arch::exception_handling
 {
   /**
    * @brief Assert a condition to be true, if not do not continue
-   * execution of the code and print the formatted message to screen.
+   * execution of the code and print the given message to screen.
    *
    * @param condition Condition we want to be true or else halt execution.
    * @param message Message that should be printed before halting the execution if the condition is not met.
diff --git a/arch/x86_64/include/arch/memory/allocator/area_frame_allocator.hpp b/arch/x86_64/include/arch/memory/allocator/area_frame_allocator.hpp
index 685babd..b8370db 100644
--- a/arch/x86_64/include/arch/memory/allocator/area_frame_allocator.hpp
+++ b/arch/x86_64/include/arch/memory/allocator/area_frame_allocator.hpp
@@ -9,7 +9,8 @@
 namespace teachos::arch::memory::allocator
 {
   /**
-   * @brief Allocates memory using memory areas read from the multiboot2 information pointer.
+   * @brief Allocates memory linearly using memory areas read from the multiboot2 information pointer and leaks any
+   * deallocated frames.
    */
   struct area_frame_allocator
   {
@@ -39,7 +40,7 @@ namespace teachos::arch::memory::allocator
      *
      * @note Simply does nothing, because the simply area frame
      * allocator implementation does not keep track of free or used frames and can therefore not deallocate, because it
-     * does not know which frames have ben alocated in the first place.
+     * does not know which frames have been alocated in the first place.
      *
      * @param physical_frame Previously allocated physical_frame that should be deallocated.
      */
diff --git a/arch/x86_64/include/arch/memory/allocator/physical_frame.hpp b/arch/x86_64/include/arch/memory/allocator/physical_frame.hpp
index c323c10..7f04042 100644
--- a/arch/x86_64/include/arch/memory/allocator/physical_frame.hpp
+++ b/arch/x86_64/include/arch/memory/allocator/physical_frame.hpp
@@ -45,7 +45,7 @@ namespace teachos::arch::memory::allocator
     auto static containing_address(physical_address address) -> physical_frame;
 
     /**
-     * @brief Evaluates the start address of the physical frame.
+     * @brief Get the start address of this physical frame.
      *
      * @return Start address of the physical frame.
      */
diff --git a/arch/x86_64/include/arch/memory/allocator/tiny_frame_allocator.hpp b/arch/x86_64/include/arch/memory/allocator/tiny_frame_allocator.hpp
index 5a9b772..1ceb74d 100644
--- a/arch/x86_64/include/arch/memory/allocator/tiny_frame_allocator.hpp
+++ b/arch/x86_64/include/arch/memory/allocator/tiny_frame_allocator.hpp
@@ -14,7 +14,9 @@ namespace teachos::arch::memory::allocator
   }
 
   /**
-   * @brief Allocates memory using memory areas read from the multiboot2 information pointer.
+   * @brief Allocates memory using memory areas read from the multiboot2 information pointer. Does not allocate its own
+   * frames, but uses the necessary three frames provided by another allocator to map one virtual level 1 page entry and
+   * the necessary upper layers.
    */
   struct tiny_frame_allocator
   {
diff --git a/arch/x86_64/include/arch/memory/cpu/control_register.hpp b/arch/x86_64/include/arch/memory/cpu/control_register.hpp
index 9b0a4d5..e11813d 100644
--- a/arch/x86_64/include/arch/memory/cpu/control_register.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/control_register.hpp
@@ -27,14 +27,14 @@ namespace teachos::arch::memory::cpu
   };
 
   /**
-   * @brief Control register 2 flags that can be set.
+   * @brief Control register 0 flags that can be set.
    *
    * @note Modifies the basic operation of the processor. Only the most important extensions are listed below, the rest
    * are excluded for brevity. See https://en.wikipedia.org/wiki/Control_register#CR0 for more information.
    */
-  enum struct cr2_flags : uint64_t
+  enum struct cr0_flags : uint64_t
   {
-    PROTECTED_MODE_ENABLED = 1U << 0U,  ///< System is in protected moe else system is in real mode.
+    PROTECTED_MODE_ENABLED = 1U << 0U,  ///< System is in protected or system is in real mode.
     TASK_SWITCHED = 1U << 3U,   ///< Allows saving x87 task context upon a task switch only after x87 instruction used.
     WRITE_PROTECT = 1U << 16U,  ///< When set, the CPU cannot write to read-only pages when privilege level is 0.
     PAGING = 1U << 31U,         // Enable paging using the CR3 register.
@@ -57,14 +57,14 @@ namespace teachos::arch::memory::cpu
   auto write_control_register(control_register cr, uint64_t new_value) -> void;
 
   /**
-   * @brief Sets a specific bit in the CR2.
+   * @brief Sets a specific bit in the CR0.
    *
-   * @note This function reads the current value of the CR2 register, ORs the specified
-   * bit with the current value, and writes the updated value back to the CR2.
+   * @note This function reads the current value of the CR0 register, ORs the specified
+   * bit with the current value, and writes the updated value back to the CR0.
    *
-   * @param flag he flag to set in the CR2.
+   * @param flag he flag to set in the CR0.
    */
-  auto set_cr2_bit(cr2_flags flag) -> void;
+  auto set_cr0_bit(cr0_flags flag) -> void;
 
 }  // namespace teachos::arch::memory::cpu
 
diff --git a/arch/x86_64/include/arch/memory/cpu/msr.hpp b/arch/x86_64/include/arch/memory/cpu/msr.hpp
index 5cce816..cda70e2 100644
--- a/arch/x86_64/include/arch/memory/cpu/msr.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/msr.hpp
@@ -7,7 +7,7 @@
 namespace teachos::arch::memory::cpu
 {
   /**
-   * @brief Important Flags that can be writen into the Extended Feature Enable Register (EFER).
+   * @brief Important flags that can be writen into the Extended Feature Enable Register (EFER).
    *
    * @note EFER is a model-specific register allowing to configure CPU extensions. Only the most important extensions
    * are listed below, the rest are excluded for brevity. See https://en.wikipedia.org/wiki/Control_register#EFER for
@@ -15,22 +15,21 @@ namespace teachos::arch::memory::cpu
    */
   enum class efer_flags : uint64_t
   {
-    SCE = 1UL << 0UL,     ///< System Call Extensions
-    LME = 1UL << 8UL,     ///< Long Mode Enabled
-    LMA = 1UL << 10UL,    ///< Long Mode Active
-    NXE = 1UL << 11UL,    ///< No-Execute Enable
-    SVME = 1UL << 12UL,   ///< Secure Virtual Machine Enable
-    LMSLE = 1UL << 13UL,  ///< Long Mode Segment Limit Enable
-    FFXSR = 1UL << 14UL,  ///< Fast FXSAVE/FXSTOR
-    TCE = 1UL << 15UL,    ///< Translation Cache Extension
+    SCE = 1UL << 0UL,     ///< System Call Extensions.
+    LME = 1UL << 8UL,     ///< Long Mode Enabled.
+    LMA = 1UL << 10UL,    ///< Long Mode Active.
+    NXE = 1UL << 11UL,    ///< No-Execute Enable.
+    SVME = 1UL << 12UL,   ///< Secure Virtual Machine Enable.
+    LMSLE = 1UL << 13UL,  ///< Long Mode Segment Limit Enable.
+    FFXSR = 1UL << 14UL,  ///< Fast FXSAVE/FXSTOR.
+    TCE = 1UL << 15UL,    ///< Translation Cache Extension.
   };
 
   /**
-   * @brief Reads a 64-bit Model-Specific Register (MSR).
+   * @brief Reads a 64-bit from the Model-Specific Register (MSR).
    *
-   * @note This function reads the value of an MSR specified by the given address. It
-   * combines the lower and upper 32-bits of the MSR value and returns it as a
-   * 64-bit unsigned integer.
+   * @note This function reads the value of an MSR specified by the given address. It combines the lower and upper
+   * 32-bits of the MSR value read using the 'rdmsr' instruction and returns it as a 64-bit unsigned integer.
    *
    * @param msr The address of the MSR to read.
    * @return The 64-bit value read from the MSR.
@@ -50,7 +49,8 @@ namespace teachos::arch::memory::cpu
   auto write_msr(uint32_t msr, uint64_t new_value) -> void;
 
   /**
-   * @brief Sets a specific bit in the Extended Feature Enable Register (EFER) Model-Specific Register (MSR) register.
+   * @brief Sets a specific bit in the Extended Feature Enable Register (EFER), which is a Model-Specific Register
+   * (MSR).
    *
    * @note This function reads the current value of the EFER register, ORs the specified
    * bit with the current value, and writes the updated value back to the EFER register.
diff --git a/arch/x86_64/include/arch/memory/cpu/tlb.hpp b/arch/x86_64/include/arch/memory/cpu/tlb.hpp
index 21f09e5..075d7bb 100644
--- a/arch/x86_64/include/arch/memory/cpu/tlb.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/tlb.hpp
@@ -15,7 +15,10 @@ namespace teachos::arch::memory::cpu
   auto tlb_flush(paging::virtual_address address) -> void;
 
   /**
-   * @brief Invalidates the translation lookaside buffer (TLB) entry for all page tables
+   * @brief Invalidates the translation lookaside buffer (TLB) entry for all page tables.
+   *
+   * @note Simply reassigns the CR3 register the value of the CR3 register, causing a flush of the TLB buffer, because
+   * the system has to assume that the location of the level 4 page table moved.
    */
   auto tlb_flush_all() -> void;
 
diff --git a/arch/x86_64/include/arch/memory/heap/memory_block.hpp b/arch/x86_64/include/arch/memory/heap/memory_block.hpp
index 502d64e..b9a2254 100644
--- a/arch/x86_64/include/arch/memory/heap/memory_block.hpp
+++ b/arch/x86_64/include/arch/memory/heap/memory_block.hpp
@@ -7,7 +7,7 @@ namespace teachos::arch::memory::heap
 {
   /**
    * @brief Block containing free memory, pointing to the next free hole (nullptr) if there is none.
-   * Forms a single linked list.
+   * Forms a singly linked list of free memory blocks that we can callocate memory into.
    */
   struct memory_block
   {
diff --git a/arch/x86_64/src/memory/cpu/control_register.cpp b/arch/x86_64/src/memory/cpu/control_register.cpp
index 7624244..298874f 100644
--- a/arch/x86_64/src/memory/cpu/control_register.cpp
+++ b/arch/x86_64/src/memory/cpu/control_register.cpp
@@ -66,9 +66,9 @@ namespace teachos::arch::memory::cpu
     }
   }
 
-  auto set_cr2_bit(cr2_flags flag) -> void
+  auto set_cr0_bit(cr0_flags flag) -> void
   {
-    auto const cr2 = read_control_register(control_register::CR2);
-    write_control_register(control_register::CR2, static_cast<std::underlying_type<cr2_flags>::type>(flag) | cr2);
+    auto const cr0 = read_control_register(control_register::CR0);
+    write_control_register(control_register::CR0, static_cast<std::underlying_type<cr0_flags>::type>(flag) | cr0);
   }
 }  // namespace teachos::arch::memory::cpu
diff --git a/arch/x86_64/src/memory/main.cpp b/arch/x86_64/src/memory/main.cpp
index 34ce113..2f01c5e 100644
--- a/arch/x86_64/src/memory/main.cpp
+++ b/arch/x86_64/src/memory/main.cpp
@@ -38,7 +38,7 @@ namespace teachos::arch::memory
     auto const memory_information = multiboot::read_multiboot2();
     allocator::area_frame_allocator allocator(memory_information);
 
-    cpu::set_cr2_bit(memory::cpu::cr2_flags::WRITE_PROTECT);
+    cpu::set_cr0_bit(memory::cpu::cr0_flags::WRITE_PROTECT);
     cpu::set_efer_bit(memory::cpu::efer_flags::NXE);
 
     paging::kernel_mapper kernel(allocator, memory_information);