x86_64/cpu: implement basic interrupt handling

1 files changed, 112 insertions, 0 deletions

diff --git a/arch/x86_64/src/cpu/interrupt_stubs.S b/arch/x86_64/src/cpu/interrupt_stubs.S
new file mode 100644
index 0000000..e59bdd2
--- /dev/null
+++ b/arch/x86_64/src/cpu/interrupt_stubs.S
@@ -0,0 +1,112 @@
+.altmacro
+
+.macro ISR_WITHOUT_ERROR_CODE vector
+    .global isr\vector
+    isr\vector:
+        pushq $0
+        pushq $\vector
+        jmp common_interrupt_handler
+.endm
+
+.macro ISR_WITH_ERROR_CODE vector
+    .global isr\vector
+    isr\vector:
+        pushq $\vector
+        jmp common_interrupt_handler
+.endm
+
+.macro ISR_TABLE_ENTRY vector
+    .quad isr\vector
+.endm
+
+.section .rodata
+.global isr_stub_table
+.align 16
+
+isr_stub_table:
+.set i, 0
+.rept 256
+    ISR_TABLE_ENTRY %i
+    .set i, i + 1
+.endr
+
+
+.section .text
+
+common_interrupt_handler:
+    push %rax
+    push %rbx
+    push %rcx
+    push %rdx
+    push %rbp
+    push %rsi
+    push %rdi
+    push %r8
+    push %r9
+    push %r10
+    push %r11
+    push %r12
+    push %r13
+    push %r14
+    push %r15
+
+    mov %rsp, %rdi
+    call interrupt_dispatch
+
+    pop %r15
+    pop %r14
+    pop %r13
+    pop %r12
+    pop %r11
+    pop %r10
+    pop %r9
+    pop %r8
+    pop %rdi
+    pop %rsi
+    pop %rbp
+    pop %rdx
+    pop %rcx
+    pop %rbx
+    pop %rax
+
+    add $16, %rsp
+    iretq
+
+ISR_WITHOUT_ERROR_CODE 0
+ISR_WITHOUT_ERROR_CODE 1
+ISR_WITHOUT_ERROR_CODE 2
+ISR_WITHOUT_ERROR_CODE 3
+ISR_WITHOUT_ERROR_CODE 4
+ISR_WITHOUT_ERROR_CODE 5
+ISR_WITHOUT_ERROR_CODE 6
+ISR_WITHOUT_ERROR_CODE 7
+ISR_WITH_ERROR_CODE 8
+ISR_WITHOUT_ERROR_CODE 9
+ISR_WITH_ERROR_CODE 10
+ISR_WITH_ERROR_CODE 11
+ISR_WITH_ERROR_CODE 12
+ISR_WITH_ERROR_CODE 13
+ISR_WITH_ERROR_CODE 14
+ISR_WITHOUT_ERROR_CODE 15
+ISR_WITHOUT_ERROR_CODE 16
+ISR_WITH_ERROR_CODE 17
+ISR_WITHOUT_ERROR_CODE 18
+ISR_WITHOUT_ERROR_CODE 19
+ISR_WITHOUT_ERROR_CODE 20
+ISR_WITH_ERROR_CODE 21
+ISR_WITHOUT_ERROR_CODE 22
+ISR_WITHOUT_ERROR_CODE 23
+ISR_WITHOUT_ERROR_CODE 24
+ISR_WITHOUT_ERROR_CODE 25
+ISR_WITHOUT_ERROR_CODE 26
+ISR_WITHOUT_ERROR_CODE 27
+ISR_WITHOUT_ERROR_CODE 28
+ISR_WITH_ERROR_CODE 29
+ISR_WITH_ERROR_CODE 30
+ISR_WITHOUT_ERROR_CODE 31
+
+.set i, 32
+.rept 256 - 32
+    ISR_WITHOUT_ERROR_CODE %i
+    .set i, i + 1
+.endr