IN_PROGRESS implement gdt initialization

4 files changed, 152 insertions, 0 deletions

diff --git a/arch/x86_64/src/kernel/cpu/control_register.cpp b/arch/x86_64/src/kernel/cpu/control_register.cpp
new file mode 100644
index 0000000..3051bae
--- /dev/null
+++ b/arch/x86_64/src/kernel/cpu/control_register.cpp
@@ -0,0 +1,72 @@
+#include "arch/kernel/cpu/control_register.hpp"
+
+#include "arch/exception_handling/panic.hpp"
+
+#include <type_traits>
+
+namespace teachos::arch::memory::cpu
+{
+  auto read_control_register(control_register cr) -> uint64_t
+  {
+    uint64_t current_value;
+    switch (cr)
+    {
+      case control_register::CR0:
+        asm volatile("mov %%cr0, %[output]" : [output] "=r"(current_value));
+        break;
+      case control_register::CR2:
+        asm volatile("mov %%cr2, %[output]" : [output] "=r"(current_value));
+        break;
+      case control_register::CR3:
+        asm volatile("mov %%cr3, %[output]" : [output] "=r"(current_value));
+        break;
+      case control_register::CR4:
+        asm volatile("mov %%cr4, %[output]" : [output] "=r"(current_value));
+        break;
+      default:
+        exception_handling::panic("[Control Register] Attempted to read non-existent or reserved control register");
+        break;
+    }
+    return current_value;
+  }
+
+  auto write_control_register(control_register cr, uint64_t new_value) -> void
+  {
+    switch (cr)
+    {
+      case control_register::CR0:
+        asm volatile("mov %[input], %%cr0"
+                     : /* no output from call */
+                     : [input] "r"(new_value)
+                     : "memory");
+        break;
+      case control_register::CR2:
+        asm volatile("mov %[input], %%cr2"
+                     : /* no output from call */
+                     : [input] "r"(new_value)
+                     : "memory");
+        break;
+      case control_register::CR3:
+        asm volatile("mov %[input], %%cr3"
+                     : /* no output from call */
+                     : [input] "r"(new_value)
+                     : "memory");
+        break;
+      case control_register::CR4:
+        asm volatile("mov %[input], %%cr4"
+                     : /* no output from call */
+                     : [input] "r"(new_value)
+                     : "memory");
+        break;
+      default:
+        exception_handling::panic("[Control Register] Attempted to write non-existent or reserved control register");
+        break;
+    }
+  }
+
+  auto set_cr0_bit(cr0_flags flag) -> void
+  {
+    auto const cr0 = read_control_register(control_register::CR0);
+    write_control_register(control_register::CR0, static_cast<std::underlying_type<cr0_flags>::type>(flag) | cr0);
+  }
+}  // namespace teachos::arch::memory::cpu
diff --git a/arch/x86_64/src/kernel/cpu/msr.cpp b/arch/x86_64/src/kernel/cpu/msr.cpp
new file mode 100644
index 0000000..082bca9
--- /dev/null
+++ b/arch/x86_64/src/kernel/cpu/msr.cpp
@@ -0,0 +1,31 @@
+#include "arch/kernel/cpu/msr.hpp"
+
+namespace teachos::arch::memory::cpu
+{
+  namespace
+  {
+    auto constexpr IA32_EFER_ADDRESS = 0xC0000080;
+  }
+
+  auto read_msr(uint32_t msr) -> uint64_t
+  {
+    uint32_t low, high;
+    asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(msr));
+    return (static_cast<uint64_t>(high) << 32) | low;
+  }
+
+  auto write_msr(uint32_t msr, uint64_t value) -> void
+  {
+    uint32_t low = value & 0xFFFFFFFF;
+    uint32_t high = value >> 32;
+    asm volatile("wrmsr"
+                 : /* no output from call */
+                 : "c"(msr), "a"(low), "d"(high));
+  }
+
+  auto set_efer_bit(efer_flags flag) -> void
+  {
+    auto const efer = read_msr(IA32_EFER_ADDRESS);
+    write_msr(IA32_EFER_ADDRESS, static_cast<std::underlying_type<efer_flags>::type>(flag) | efer);
+  }
+}  // namespace teachos::arch::memory::cpu
diff --git a/arch/x86_64/src/kernel/cpu/ss.cpp b/arch/x86_64/src/kernel/cpu/ss.cpp
new file mode 100644
index 0000000..b7e52e1
--- /dev/null
+++ b/arch/x86_64/src/kernel/cpu/ss.cpp
@@ -0,0 +1,33 @@
+#include "arch/kernel/cpu/ss.hpp"
+
+namespace teachos::arch::memory::cpu
+{
+  segment_selector::segment_selector(uint16_t index, std::bitset<1U> table_indicator,
+                                     std::bitset<2U> requested_privilege_level)
+      : index(index)
+      , table_indicator(table_indicator)
+      , requested_privilege_level(requested_privilege_level)
+  {
+    // Nothing to do
+  }
+
+  auto segment_selector::to_uint16() const -> uint16_t
+  {
+    return static_cast<uint16_t>((index << 3) | (table_indicator.to_ulong() << 2) |
+                                 requested_privilege_level.to_ulong());
+  }
+
+  auto read_ss() -> uint16_t
+  {
+    uint16_t ss;
+    __asm__("mov %%ss, %0" : "=r"(ss));
+    return ss;
+  }
+
+  auto write_ss(segment_selector selector) -> void
+  {
+    uint16_t ss = selector.to_uint16();
+    __asm__("mov %0, %%ss" ::"r"(ss));
+  }
+
+}  // namespace teachos::arch::memory::cpu
\ No newline at end of file
diff --git a/arch/x86_64/src/kernel/cpu/tlb.cpp b/arch/x86_64/src/kernel/cpu/tlb.cpp
new file mode 100644
index 0000000..e753c2c
--- /dev/null
+++ b/arch/x86_64/src/kernel/cpu/tlb.cpp
@@ -0,0 +1,16 @@
+#include "arch/kernel/cpu/tlb.hpp"
+
+#include "arch/kernel/cpu/control_register.hpp"
+
+namespace teachos::arch::memory::cpu
+{
+  auto tlb_flush(paging::virtual_address address) -> void
+  {
+    asm volatile("invlpg (%[input])" : /* no output from call */ : [input] "r"(address) : "memory");
+  }
+
+  auto tlb_flush_all() -> void
+  {
+    write_control_register(cpu::control_register::CR3, read_control_register(cpu::control_register::CR3));
+  }
+}  // namespace teachos::arch::memory::cpu