Move tlb into seperate subfolder and create cr3 header for reading and writing.

2 files changed, 31 insertions, 0 deletions

diff --git a/arch/x86_64/src/memory/cpu/cr3.cpp b/arch/x86_64/src/memory/cpu/cr3.cpp
new file mode 100644
index 0000000..7e48d40
--- /dev/null
+++ b/arch/x86_64/src/memory/cpu/cr3.cpp
@@ -0,0 +1,23 @@
+#include "arch/memory/cpu/cr3.hpp"
+
+#include "arch/exception_handling/assert.hpp"
+
+namespace teachos::arch::memory::cpu
+{
+  auto read_cr3_register() -> allocator::physical_address
+  {
+    allocator::physical_address cr3;
+    asm volatile("movq %%cr3, %[output]" : [output] "=r"(cr3) : /* no input into call */ : "memory");
+    return cr3;
+  }
+
+  auto write_cr3_register(allocator::physical_address new_p4_table_address) -> void
+  {
+    exception_handling::assert(new_p4_table_address % allocator::PAGE_FRAME_SIZE == 0U,
+                               "[CR3] Physical address to be written into register must be page aligned");
+    asm volatile("movq %[input], %%cr3"
+                 : /* no output from call */
+                 : [input] "r"(new_p4_table_address)
+                 : "memory");
+  }
+}  // namespace teachos::arch::memory::cpu
diff --git a/arch/x86_64/src/memory/cpu/tlb.cpp b/arch/x86_64/src/memory/cpu/tlb.cpp
new file mode 100644
index 0000000..bac46b7
--- /dev/null
+++ b/arch/x86_64/src/memory/cpu/tlb.cpp
@@ -0,0 +1,8 @@
+#include "arch/memory/cpu/tlb.hpp"
+
+namespace teachos::arch::memory::cpu
+{
+  auto tlb_flush(paging::virtual_address address) -> void { asm volatile("invlpg (%0)" ::"r"(address) : "memory"); }
+
+  auto tlb_flush_all() -> void { tlb_flush(PAGE_TABLE_LEVEL_4_ADDRESS); }
+}  // namespace teachos::arch::memory::cpu