Finish control register and adjust msr

6 files changed, 42 insertions, 42 deletions

diff --git a/arch/x86_64/CMakeLists.txt b/arch/x86_64/CMakeLists.txt
index ee0141e..f868b4e 100644
--- a/arch/x86_64/CMakeLists.txt
+++ b/arch/x86_64/CMakeLists.txt
@@ -54,6 +54,7 @@ target_sources("_memory" PRIVATE
   "src/memory/paging/inactive_page_table.cpp"
   "src/memory/cpu/tlb.cpp"
   "src/memory/cpu/control_register.cpp"
+  "src/memory/cpu/msr.cpp"
 )
 
 #[============================================================================[
diff --git a/arch/x86_64/include/arch/memory/cpu/control_register.hpp b/arch/x86_64/include/arch/memory/cpu/control_register.hpp
index b48e48c..4988036 100644
--- a/arch/x86_64/include/arch/memory/cpu/control_register.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/control_register.hpp
@@ -32,7 +32,7 @@ namespace teachos::arch::memory::cpu
    * @note Modifies the basic operation of the processor. Only the most important extensions are listed below, the rest
    * are excluded for brevity. See https://en.wikipedia.org/wiki/Control_register#CR0 for more information.
    */
-  enum struct cr2_flags : uint32_t
+  enum struct cr2_flags : uint64_t
   {
     PROTECTED_MODE_ENABLED = 1U << 0U,  ///< System is in protected moe else system is in real mode.
     TASK_SWITCHED = 1U << 3U,   ///< Allows saving x87 task context upon a task switch only after x87 instruction used.
@@ -43,28 +43,28 @@ namespace teachos::arch::memory::cpu
   /**
    * @brief Reads the value of the given control register.
    *
-   * @note The cr3 register value represents the physical address of the level 4 page table used for paging in the
-   * system. Therefore reading this value allows to access the level 4 page table directly. Instead of over the virtual
-   * address 0xffffffff'fffff000, which then has to be first translated into a physical address.
-   *
-   * @return Physical address the level 4 page table is located at.
-   */
-
-  /**
-   * @brief Reads the value of the given control register.
-   *
    * @param cr Control register that should be read.
    * @return Value of the control register.
    */
-  auto read_control_register(control_register cr) -> std::size_t;
+  auto read_control_register(control_register cr) -> uint64_t;
 
   /**
-   * @brief Writes the given value into the given control register.
+   * @brief Sets a specific bit in the Extended Feature Enable Register (EFER) Model-Specific Register (MSR) register.
    *
    * @param cr Control register that should be written.
    * @param new_value New value that should be written.
    */
-  auto write_control_register(control_register cr, std::size_t new_value) -> void;
+  auto write_control_register(control_register cr, uint64_t new_value) -> void;
+
+  /**
+   * @brief Sets a specific bit in the CR2.
+   *
+   * @note This function reads the current value of the CR2 register, ORs the specified
+   * bit with the current value, and writes the updated value back to the CR2.
+   *
+   * @param flag he flag to set in the CR2.
+   */
+  auto set_cr2_bit(cr2_flags flag) -> void;
 }  // namespace teachos::arch::memory::cpu
 
 #endif  // TEACHOS_ARCH_X86_64_MEMORY_CPU_CR3_HPP
diff --git a/arch/x86_64/include/arch/memory/cpu/msr.hpp b/arch/x86_64/include/arch/memory/cpu/msr.hpp
index 1403995..49e9bcf 100644
--- a/arch/x86_64/include/arch/memory/cpu/msr.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/msr.hpp
@@ -35,7 +35,7 @@ namespace teachos::arch::memory::cpu
    * @param msr The address of the MSR to read.
    * @return The 64-bit value read from the MSR.
    */
-  auto read_msr(uint32_t msr) -> void;
+  auto read_msr(uint32_t msr) -> uint64_t;
 
   /**
    * @brief Writes a 64-bit value to a Model-Specific Register (MSR).
@@ -58,17 +58,6 @@ namespace teachos::arch::memory::cpu
    * @param flag The flag to set in the EFER register.
    */
   auto set_efer_bit(efer_flags flag) -> void;
-
-  /**
-   * @brief Enables the No-Execute Enable (NXE) bit in the Extended Feature Enable Register (EFER).
-   *
-   * @note This function reads the current value of the EFER register, enables the NXE bit
-   * (bit 11), and writes the updated value back to the EFER register. Enabling the NXE
-   * bit allows the processor to support No-Execute memory regions, which are required
-   * for certain memory protection features like Data Execution Prevention (DEP).
-   */
-  auto enable_nxe_bit() -> void;
-
 }  // namespace teachos::arch::memory::cpu
 
 #endif  // TEACHOS_ARCH_X86_64_MEMORY_CPU_NXE_HPP
\ No newline at end of file
diff --git a/arch/x86_64/src/kernel/main.cpp b/arch/x86_64/src/kernel/main.cpp
index c111f22..ea1a157 100644
--- a/arch/x86_64/src/kernel/main.cpp
+++ b/arch/x86_64/src/kernel/main.cpp
@@ -2,6 +2,7 @@
 
 #include "arch/exception_handling/assert.hpp"
 #include "arch/memory/allocator/area_frame_allocator.hpp"
+#include "arch/memory/cpu/msr.hpp"
 #include "arch/memory/multiboot/reader.hpp"
 #include "arch/memory/paging/kernel_mapper.hpp"
 #include "arch/memory/paging/temporary_page.hpp"
@@ -20,6 +21,9 @@ namespace teachos::arch::kernel
     auto const memory_information = memory::multiboot::read_multiboot2();
     memory::allocator::area_frame_allocator allocator(memory_information);
 
+    memory::cpu::set_cr2_bit(memory::cpu::cr2_flags::WRITE_PROTECT);
+    memory::cpu::set_efer_bit(memory::cpu::efer_flags::NXE);
+
     memory::paging::kernel_mapper kernel(allocator, memory_information);
     kernel.remap_kernel();
     video::vga::text::write("Kernel remapping successfull", video::vga::text::common_attributes::green_on_black);
diff --git a/arch/x86_64/src/memory/cpu/control_register.cpp b/arch/x86_64/src/memory/cpu/control_register.cpp
index 38a887c..7624244 100644
--- a/arch/x86_64/src/memory/cpu/control_register.cpp
+++ b/arch/x86_64/src/memory/cpu/control_register.cpp
@@ -2,24 +2,26 @@
 
 #include "arch/exception_handling/assert.hpp"
 
+#include <type_traits>
+
 namespace teachos::arch::memory::cpu
 {
-  auto read_control_register(control_register cr) -> std::size_t
+  auto read_control_register(control_register cr) -> uint64_t
   {
-    std::size_t current_value;
+    uint64_t current_value;
     switch (cr)
     {
       case control_register::CR0:
-        asm volatile("movq %%cr0, %[output]" : [output] "=r"(current_value));
+        asm volatile("mov %%cr0, %[output]" : [output] "=r"(current_value));
         break;
       case control_register::CR2:
-        asm volatile("movq %%cr2, %[output]" : [output] "=r"(current_value));
+        asm volatile("mov %%cr2, %[output]" : [output] "=r"(current_value));
         break;
       case control_register::CR3:
-        asm volatile("movq %%cr3, %[output]" : [output] "=r"(current_value));
+        asm volatile("mov %%cr3, %[output]" : [output] "=r"(current_value));
         break;
       case control_register::CR4:
-        asm volatile("movq %%cr4, %[output]" : [output] "=r"(current_value));
+        asm volatile("mov %%cr4, %[output]" : [output] "=r"(current_value));
         break;
       default:
         exception_handling::assert(false,
@@ -29,30 +31,30 @@ namespace teachos::arch::memory::cpu
     return current_value;
   }
 
-  auto write_control_register(control_register cr, std::size_t new_value) -> void
+  auto write_control_register(control_register cr, uint64_t new_value) -> void
   {
     switch (cr)
     {
       case control_register::CR0:
-        asm volatile("movq %[input], %%cr0"
+        asm volatile("mov %[input], %%cr0"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
         break;
       case control_register::CR2:
-        asm volatile("movq %[input], %%cr2"
+        asm volatile("mov %[input], %%cr2"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
         break;
       case control_register::CR3:
-        asm volatile("movq %[input], %%cr3"
+        asm volatile("mov %[input], %%cr3"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
         break;
       case control_register::CR4:
-        asm volatile("movq %[input], %%cr4"
+        asm volatile("mov %[input], %%cr4"
                      : /* no output from call */
                      : [input] "r"(new_value)
                      : "memory");
@@ -63,4 +65,10 @@ namespace teachos::arch::memory::cpu
         break;
     }
   }
+
+  auto set_cr2_bit(cr2_flags flag) -> void
+  {
+    auto const cr2 = read_control_register(control_register::CR2);
+    write_control_register(control_register::CR2, static_cast<std::underlying_type<cr2_flags>::type>(flag) | cr2);
+  }
 }  // namespace teachos::arch::memory::cpu
diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp
index 6e3d1d3..b83f902 100644
--- a/arch/x86_64/src/memory/cpu/msr.cpp
+++ b/arch/x86_64/src/memory/cpu/msr.cpp
@@ -4,7 +4,7 @@ namespace teachos::arch::memory::cpu
 {
   namespace
   {
-    constexpr uint32_t IA32_EFER_ADDRESS = 0xC0000080;
+    auto constexpr IA32_EFER_ADDRESS = 0xC0000080;
   }
 
   auto read_msr(uint32_t msr) -> uint64_t
@@ -25,9 +25,7 @@ namespace teachos::arch::memory::cpu
 
   auto set_efer_bit(efer_flags flag) -> void
   {
-    uint64_t const efer = read_msr(IA32_EFER_ADDRESS);
-    write_msr(IA32_EFER_ADDRESS, static_cast<uint64_t>(flag) | efer);
+    auto const efer = read_msr(IA32_EFER_ADDRESS);
+    write_msr(IA32_EFER_ADDRESS, static_cast<std::underlying_type<efer_flags>::type>(flag) | efer);
   }
-
-  auto enable_nxe_bit() -> void { set_efer_bit(efer_flags::NXE); }
 }  // namespace teachos::arch::memory::cpu