Merge branch 'feat_inital_context_switching' into 'develop_ba'

Implement Context Switching

See merge request teachos/kernel!6

10 files changed, 54 insertions, 0 deletions

diff --git a/docs/arch/x86_64/kernel/cpu.rst b/docs/arch/x86_64/kernel/cpu.rst
new file mode 100644
index 0000000..da3dfc0
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu.rst
@@ -0,0 +1,9 @@
+Kernel CPU Registers
+===========
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+   :glob:
+
+   cpu/*
diff --git a/docs/arch/x86_64/kernel/cpu/call.rst b/docs/arch/x86_64/kernel/cpu/call.rst
new file mode 100644
index 0000000..33d15ec
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/call.rst
@@ -0,0 +1,5 @@
+Far Call
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/call.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/control_register.rst b/docs/arch/x86_64/kernel/cpu/control_register.rst
new file mode 100644
index 0000000..a45c6d9
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/control_register.rst
@@ -0,0 +1,5 @@
+Control Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/control_register.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/gdtr.rst b/docs/arch/x86_64/kernel/cpu/gdtr.rst
new file mode 100644
index 0000000..41c0f6b
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/gdtr.rst
@@ -0,0 +1,5 @@
+Global Descriptor Table Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/gdtr.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/idtr.rst b/docs/arch/x86_64/kernel/cpu/idtr.rst
new file mode 100644
index 0000000..b4c4bb0
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/idtr.rst
@@ -0,0 +1,5 @@
+Interrupt Descriptor Table Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/idtr.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/if.rst b/docs/arch/x86_64/kernel/cpu/if.rst
new file mode 100644
index 0000000..2dd07b4
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/if.rst
@@ -0,0 +1,5 @@
+Interrupt Flag
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/if.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/msr.rst b/docs/arch/x86_64/kernel/cpu/msr.rst
new file mode 100644
index 0000000..75c4f47
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/msr.rst
@@ -0,0 +1,5 @@
+Model Specific Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/msr.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/segment_register.rst b/docs/arch/x86_64/kernel/cpu/segment_register.rst
new file mode 100644
index 0000000..8159369
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/segment_register.rst
@@ -0,0 +1,5 @@
+CPU Segment Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/segment_register.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/tlb.rst b/docs/arch/x86_64/kernel/cpu/tlb.rst
new file mode 100644
index 0000000..1ceec1d
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/tlb.rst
@@ -0,0 +1,5 @@
+Translation Lookaside Buffer
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/tlb.hpp
+
diff --git a/docs/arch/x86_64/kernel/cpu/tr.rst b/docs/arch/x86_64/kernel/cpu/tr.rst
new file mode 100644
index 0000000..a2b234b
--- /dev/null
+++ b/docs/arch/x86_64/kernel/cpu/tr.rst
@@ -0,0 +1,5 @@
+Task Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/kernel/cpu/tr.hpp
+