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-rw-r--r--arch/x86_64/include/arch/memory/paging/active_page_table.hpp27
-rw-r--r--arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp12
2 files changed, 24 insertions, 15 deletions
diff --git a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp
index e876798..e2c205b 100644
--- a/arch/x86_64/include/arch/memory/paging/active_page_table.hpp
+++ b/arch/x86_64/include/arch/memory/paging/active_page_table.hpp
@@ -10,6 +10,7 @@
namespace teachos::arch::memory::paging
{
+ std::size_t constexpr PAGE_TABLE_LEVEL_4_ADDRESS = 0xffffffff'fffff000;
/**
* @brief Currently active level 4 page table, is used to ensure there is only ever one valid instance and it cannot
@@ -17,7 +18,7 @@ namespace teachos::arch::memory::paging
*/
struct active_page_table
{
- typedef void (*function)(active_page_table * active_page_table);
+ typedef void (*function)(active_page_table & active_page_table);
/**
* @brief Creates a single instance of an active level 4 page table table and returns the created instance or
@@ -54,6 +55,18 @@ namespace teachos::arch::memory::paging
auto translate_huge_page(virtual_page page) -> std::optional<allocator::physical_frame>;
/**
+ * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained
+ * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction.
+ *
+ * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for
+ * that page.
+ */
+ static auto invalidate_page_cache(virtual_address address) -> void
+ {
+ asm volatile("invlpg (%0)" ::"r"(address) : "memory");
+ }
+
+ /**
* @brief Maps a virtual page to a physical frame in the page table with the specified flags.
*
* @note Allocates and maps an entry in every page level if it does not exists yet down to level 1. If the level 1
@@ -181,18 +194,6 @@ namespace teachos::arch::memory::paging
active_page_table & operator=(active_page_table const &) = delete;
/**
- * @brief Invalidates any translation lookaside buffer (TLB) entry for the page table the given address is cotained
- * in. See https://www.felixcloutier.com/x86/invlpg for more information on the used x86 instruction.
- *
- * @param address Memory address, which will be used to determine the contained page and flush the TLB entry for
- * that page.
- */
- static auto invalidate_page_cache(virtual_address address) -> void
- {
- asm volatile("invlpg (%0)" ::"r"(address) : "memory");
- }
-
- /**
* @brief Unmaps specific page at the current internal handle level.
*
* @tparam T Type constraint of the allocator, being that is follows the given concept and contains an allocate and
diff --git a/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp b/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp
index 085344a..0583692 100644
--- a/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp
+++ b/arch/x86_64/include/arch/memory/paging/kernel_mapper.hpp
@@ -7,8 +7,16 @@
namespace teachos::arch::memory::paging
{
- auto with(inactive_page_table inactive_page_table, temporary_page temporary_page, active_page_table::function f,
- active_page_table & active_page_table) -> void;
+ struct kernel_mapper
+ {
+ kernel_mapper(active_page_table & active_table);
+
+ auto with(inactive_page_table inactive_page_table, temporary_page temporary_page,
+ active_page_table::function f) -> void;
+
+ private:
+ active_page_table & active_table;
+ };
} // namespace teachos::arch::memory::paging
#endif // TEACHOS_ARCH_X86_64_MEMORY_PAGING_KERNEL_MAPPER_HPP