2 files changed, 15 insertions, 26 deletions
diff --git a/arch/x86_64/include/arch/memory/cpu/control_register.hpp b/arch/x86_64/include/arch/memory/cpu/control_register.hpp
index b48e48c..4988036 100644
--- a/arch/x86_64/include/arch/memory/cpu/control_register.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/control_register.hpp
@@ -32,7 +32,7 @@ namespace teachos::arch::memory::cpu
    * @note Modifies the basic operation of the processor. Only the most important extensions are listed below, the rest
    * are excluded for brevity. See https://en.wikipedia.org/wiki/Control_register#CR0 for more information.
    */
-  enum struct cr2_flags : uint32_t
+  enum struct cr2_flags : uint64_t
   {
     PROTECTED_MODE_ENABLED = 1U << 0U,  ///< System is in protected moe else system is in real mode.
     TASK_SWITCHED = 1U << 3U,   ///< Allows saving x87 task context upon a task switch only after x87 instruction used.
@@ -43,28 +43,28 @@ namespace teachos::arch::memory::cpu
   /**
    * @brief Reads the value of the given control register.
    *
-   * @note The cr3 register value represents the physical address of the level 4 page table used for paging in the
-   * system. Therefore reading this value allows to access the level 4 page table directly. Instead of over the virtual
-   * address 0xffffffff'fffff000, which then has to be first translated into a physical address.
-   *
-   * @return Physical address the level 4 page table is located at.
-   */
-
-  /**
-   * @brief Reads the value of the given control register.
-   *
    * @param cr Control register that should be read.
    * @return Value of the control register.
    */
-  auto read_control_register(control_register cr) -> std::size_t;
+  auto read_control_register(control_register cr) -> uint64_t;
 
   /**
-   * @brief Writes the given value into the given control register.
+   * @brief Sets a specific bit in the Extended Feature Enable Register (EFER) Model-Specific Register (MSR) register.
    *
    * @param cr Control register that should be written.
    * @param new_value New value that should be written.
    */
-  auto write_control_register(control_register cr, std::size_t new_value) -> void;
+  auto write_control_register(control_register cr, uint64_t new_value) -> void;
+
+  /**
+   * @brief Sets a specific bit in the CR2.
+   *
+   * @note This function reads the current value of the CR2 register, ORs the specified
+   * bit with the current value, and writes the updated value back to the CR2.
+   *
+   * @param flag he flag to set in the CR2.
+   */
+  auto set_cr2_bit(cr2_flags flag) -> void;
 }  // namespace teachos::arch::memory::cpu
 
 #endif  // TEACHOS_ARCH_X86_64_MEMORY_CPU_CR3_HPP
diff --git a/arch/x86_64/include/arch/memory/cpu/msr.hpp b/arch/x86_64/include/arch/memory/cpu/msr.hpp
index 1403995..49e9bcf 100644
--- a/arch/x86_64/include/arch/memory/cpu/msr.hpp
+++ b/arch/x86_64/include/arch/memory/cpu/msr.hpp
@@ -35,7 +35,7 @@ namespace teachos::arch::memory::cpu
    * @param msr The address of the MSR to read.
    * @return The 64-bit value read from the MSR.
    */
-  auto read_msr(uint32_t msr) -> void;
+  auto read_msr(uint32_t msr) -> uint64_t;
 
   /**
    * @brief Writes a 64-bit value to a Model-Specific Register (MSR).
@@ -58,17 +58,6 @@ namespace teachos::arch::memory::cpu
    * @param flag The flag to set in the EFER register.
    */
   auto set_efer_bit(efer_flags flag) -> void;
-
-  /**
-   * @brief Enables the No-Execute Enable (NXE) bit in the Extended Feature Enable Register (EFER).
-   *
-   * @note This function reads the current value of the EFER register, enables the NXE bit
-   * (bit 11), and writes the updated value back to the EFER register. Enabling the NXE
-   * bit allows the processor to support No-Execute memory regions, which are required
-   * for certain memory protection features like Data Execution Prevention (DEP).
-   */
-  auto enable_nxe_bit() -> void;
-
 }  // namespace teachos::arch::memory::cpu
 
 #endif  // TEACHOS_ARCH_X86_64_MEMORY_CPU_NXE_HPP
 \ No newline at end of file