diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86_64/include/arch/memory/cpu/msr.hpp | 69 | ||||
| -rw-r--r-- | arch/x86_64/src/memory/cpu/msr.cpp | 29 |
2 files changed, 98 insertions, 0 deletions
diff --git a/arch/x86_64/include/arch/memory/cpu/msr.hpp b/arch/x86_64/include/arch/memory/cpu/msr.hpp new file mode 100644 index 0000000..662f3ac --- /dev/null +++ b/arch/x86_64/include/arch/memory/cpu/msr.hpp @@ -0,0 +1,69 @@ +#ifndef TEACHOS_ARCH_X86_64_MEMORY_CPU_NXE_HPP +#define TEACHOS_ARCH_X86_64_MEMORY_CPU_NXE_HPP + +#include <bitset> +#include <cstdint> + +namespace teachos::arch::memory::cpu +{ + constexpr uint32_t IA32_EFER = 0xC0000080; + + enum class msr_flags : uint64_t + { + SCE = 1U << 0ULL, ///< System Call Extensions + LME = 1U << 8ULL, ///< Long Mode Enabled + LMA = 1U << 10ULL, ///< Long Mode Active + NXE = 1U << 11ULL, ///< No-Execute Enable + SVME = 1U << 12ULL, ///< Secure Virtual Machine Enable + LMSLE = 1U << 13ULL, ///< Secure Virtual Machine Enable + FFXSR = 1U << 14ULL, ///< fast FXSAVE/FXSTOR + TCE = 1U << 15ULL, ///< Translation Cache Extension + }; + + /** + * @brief Reads a 64-bit Model-Specific Register (MSR). + * + * This function reads the value of an MSR specified by the given address. It + * combines the lower and upper 32-bits of the MSR value and returns it as a + * 64-bit unsigned integer. + * + * @param msr The address of the MSR to read. + * @return The 64-bit value read from the MSR. + */ + uint64_t read_msr(uint32_t msr); + + /** + * @brief Writes a 64-bit value to a Model-Specific Register (MSR). + * + * This function writes a 64-bit value to the MSR specified by the given address. + * It splits the 64-bit value into two 32-bit parts and writes them using the + * `wrmsr` instruction. + * + * @param msr The address of the MSR to write to. + * @param value The 64-bit value to write to the MSR. + */ + void write_msr(uint32_t msr, uint64_t value); + + /** + * @brief Sets a specific bit in the MSR register. + * + * This function reads the current value of the EFER register, ORs the specified + * bit with the current value, and writes the updated value back to the EFER register. + * + * @param flag The flag to set in the EFER register. + */ + void set_msr_bit(msr_flags flag); + + /** + * @brief Enables the No-Execute Enable (NXE) bit in the Extended Feature Enable Register (EFER). + * + * This function reads the current value of the EFER register, enables the NXE bit + * (bit 11), and writes the updated value back to the EFER register. Enabling the NXE + * bit allows the processor to support No-Execute memory regions, which are required + * for certain memory protection features like Data Execution Prevention (DEP). + */ + void enable_nxe_bit(); + +} // namespace teachos::arch::memory::cpu + +#endif // TEACHOS_ARCH_X86_64_MEMORY_CPU_NXE_HPP
\ No newline at end of file diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp new file mode 100644 index 0000000..3a917c9 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/msr.cpp @@ -0,0 +1,29 @@ +#include "arch/memory/cpu/msr.hpp" + +namespace teachos::arch::memory::cpu +{ + uint64_t read_msr(uint32_t msr) + { + uint32_t low, high; + asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(msr)); + return (static_cast<uint64_t>(high) << 32) | low; + } + + void write_msr(uint32_t msr, uint64_t value) + { + uint32_t low = value & 0xFFFFFFFF; + uint32_t high = value >> 32; + asm volatile("wrmsr" + : /* no output from call */ + : "c"(msr), "a"(low), "d"(high)); + } + + void set_msr_bit(msr_flags flag) + { + uint64_t efer = read_msr(IA32_EFER); + write_msr(IA32_EFER, static_cast<uint64_t>(flag) | efer); + } + + void enable_nxe_bit() { set_msr_bit(msr_flags::NXE); } + +} // namespace teachos::arch::memory::cpu |