arch/x86_64/include/arch/cpu/registers.hpp


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#ifndef TEACHOS_X86_64_CPU_REGISTERS_HPP
#define TEACHOS_X86_64_CPU_REGISTERS_HPP

#include "arch/cpu/control_register.hpp"         // IWYU pragma: export
#include "arch/cpu/model_specific_register.hpp"  // IWYU pragma: export

#include "kapi/memory.hpp"

namespace arch::cpu
{

  //! Configuration Register 0.
  //!
  //! This configuration register holds various control flags to configure the configure the basic operation of the CPU.
  using cr0 = control_register<cr0_flags, &impl::cr0_asm>;

  //! Configuration Register 2.
  //!
  //! This configuration register holds the memory address the access to which has triggered the most recent page fault.
  using cr2 = control_register<kapi::memory::linear_address, &impl::cr2_asm>;

  //! Configuration Register 3.
  //!
  //! This register holds the configuration of the virtual memory protection configuration.
  using cr3 = control_register<cr3_value, &impl::cr3_asm>;

  //! The I32_EFER (Extended Feature Enable Register) MSR
  using i32_efer = model_specific_register<ia32_efer_number, ia32_efer_flags>;

}  // namespace arch::cpu

#endif