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| author | Matteo Gmür <matteo.gmuer1@ost.ch> | 2025-06-06 17:15:32 +0200 |
|---|---|---|
| committer | Matteo Gmür <matteo.gmuer1@ost.ch> | 2025-06-06 17:15:32 +0200 |
| commit | c4ced070ab057e4be6552b2f10ec1bf35509e245 (patch) | |
| tree | 91602a7732d216bff3fbaf2d6158e965460019e5 /docs/arch/x86_64/memory/cpu | |
| parent | 3fb836101a2032e93f7b82c924ce208d7377a5ea (diff) | |
| parent | 1031a69ca5e23f2087148ad57e57506735872617 (diff) | |
| download | kernel-c4ced070ab057e4be6552b2f10ec1bf35509e245.tar.xz kernel-c4ced070ab057e4be6552b2f10ec1bf35509e245.zip | |
Merge branch 'feat_inital_context_switching' into 'develop_ba'
Implement Context Switching
See merge request teachos/kernel!6
Diffstat (limited to 'docs/arch/x86_64/memory/cpu')
| -rw-r--r-- | docs/arch/x86_64/memory/cpu/control_register.rst | 5 | ||||
| -rw-r--r-- | docs/arch/x86_64/memory/cpu/msr.rst | 5 | ||||
| -rw-r--r-- | docs/arch/x86_64/memory/cpu/tlb.rst | 5 |
3 files changed, 0 insertions, 15 deletions
diff --git a/docs/arch/x86_64/memory/cpu/control_register.rst b/docs/arch/x86_64/memory/cpu/control_register.rst deleted file mode 100644 index f087112..0000000 --- a/docs/arch/x86_64/memory/cpu/control_register.rst +++ /dev/null @@ -1,5 +0,0 @@ -CPU Control Registers -======================= - -.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/control_register.hpp - diff --git a/docs/arch/x86_64/memory/cpu/msr.rst b/docs/arch/x86_64/memory/cpu/msr.rst deleted file mode 100644 index c67d51c..0000000 --- a/docs/arch/x86_64/memory/cpu/msr.rst +++ /dev/null @@ -1,5 +0,0 @@ -CPU Model-Specific Register -======================= - -.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/msr.hpp - diff --git a/docs/arch/x86_64/memory/cpu/tlb.rst b/docs/arch/x86_64/memory/cpu/tlb.rst deleted file mode 100644 index 0d482dc..0000000 --- a/docs/arch/x86_64/memory/cpu/tlb.rst +++ /dev/null @@ -1,5 +0,0 @@ -CPU Translation Lookaside Buffer -======================= - -.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/tlb.hpp - |