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| author | Fabian Imhof <fabian.imhof@ost.ch> | 2024-11-10 10:59:22 +0000 |
|---|---|---|
| committer | Fabian Imhof <fabian.imhof@ost.ch> | 2024-11-10 10:59:22 +0000 |
| commit | 1275612382c5c9d31ed7b24a2c6d699c14a10081 (patch) | |
| tree | 367427f7d5216ca07ee1ea2198f53a335fccb811 /arch/x86_64/src/memory/cpu | |
| parent | edc11135d83ef1f8fcbc1575a290b31ccbdb7e07 (diff) | |
| download | teachos-1275612382c5c9d31ed7b24a2c6d699c14a10081.tar.xz teachos-1275612382c5c9d31ed7b24a2c6d699c14a10081.zip | |
implement model specific register calls
Diffstat (limited to 'arch/x86_64/src/memory/cpu')
| -rw-r--r-- | arch/x86_64/src/memory/cpu/msr.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/x86_64/src/memory/cpu/msr.cpp b/arch/x86_64/src/memory/cpu/msr.cpp new file mode 100644 index 0000000..3a917c9 --- /dev/null +++ b/arch/x86_64/src/memory/cpu/msr.cpp @@ -0,0 +1,29 @@ +#include "arch/memory/cpu/msr.hpp" + +namespace teachos::arch::memory::cpu +{ + uint64_t read_msr(uint32_t msr) + { + uint32_t low, high; + asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(msr)); + return (static_cast<uint64_t>(high) << 32) | low; + } + + void write_msr(uint32_t msr, uint64_t value) + { + uint32_t low = value & 0xFFFFFFFF; + uint32_t high = value >> 32; + asm volatile("wrmsr" + : /* no output from call */ + : "c"(msr), "a"(low), "d"(high)); + } + + void set_msr_bit(msr_flags flag) + { + uint64_t efer = read_msr(IA32_EFER); + write_msr(IA32_EFER, static_cast<uint64_t>(flag) | efer); + } + + void enable_nxe_bit() { set_msr_bit(msr_flags::NXE); } + +} // namespace teachos::arch::memory::cpu |
