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-rw-r--r--docs/arch/x86_64/memory/cpu/control_register.rst5
-rw-r--r--docs/arch/x86_64/memory/cpu/msr.rst5
-rw-r--r--docs/arch/x86_64/memory/cpu/tlb.rst5
3 files changed, 15 insertions, 0 deletions
diff --git a/docs/arch/x86_64/memory/cpu/control_register.rst b/docs/arch/x86_64/memory/cpu/control_register.rst
new file mode 100644
index 0000000..f087112
--- /dev/null
+++ b/docs/arch/x86_64/memory/cpu/control_register.rst
@@ -0,0 +1,5 @@
+CPU Control Registers
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/control_register.hpp
+
diff --git a/docs/arch/x86_64/memory/cpu/msr.rst b/docs/arch/x86_64/memory/cpu/msr.rst
new file mode 100644
index 0000000..c67d51c
--- /dev/null
+++ b/docs/arch/x86_64/memory/cpu/msr.rst
@@ -0,0 +1,5 @@
+CPU Model-Specific Register
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/msr.hpp
+
diff --git a/docs/arch/x86_64/memory/cpu/tlb.rst b/docs/arch/x86_64/memory/cpu/tlb.rst
new file mode 100644
index 0000000..0d482dc
--- /dev/null
+++ b/docs/arch/x86_64/memory/cpu/tlb.rst
@@ -0,0 +1,5 @@
+CPU Translation Lookaside Buffer
+=======================
+
+.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/tlb.hpp
+