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| author | Matteo Gmür <matteo.gmuer1@ost.ch> | 2024-12-04 15:32:19 +0000 |
|---|---|---|
| committer | Matteo Gmür <matteo.gmuer1@ost.ch> | 2024-12-04 15:32:21 +0000 |
| commit | 82bd19117313e6d61ab2ac03583e22b8a627f14a (patch) | |
| tree | 76c062fde474af7c4e53b524242908a694273575 /docs/arch/x86_64/memory/cpu | |
| parent | 888ae9e053973125551729ff787b8f3c4cf4e1be (diff) | |
| download | teachos-82bd19117313e6d61ab2ac03583e22b8a627f14a.tar.xz teachos-82bd19117313e6d61ab2ac03583e22b8a627f14a.zip | |
Add doxygen docs file
Diffstat (limited to 'docs/arch/x86_64/memory/cpu')
| -rw-r--r-- | docs/arch/x86_64/memory/cpu/control_register.rst | 5 | ||||
| -rw-r--r-- | docs/arch/x86_64/memory/cpu/msr.rst | 5 | ||||
| -rw-r--r-- | docs/arch/x86_64/memory/cpu/tlb.rst | 5 |
3 files changed, 15 insertions, 0 deletions
diff --git a/docs/arch/x86_64/memory/cpu/control_register.rst b/docs/arch/x86_64/memory/cpu/control_register.rst new file mode 100644 index 0000000..f087112 --- /dev/null +++ b/docs/arch/x86_64/memory/cpu/control_register.rst @@ -0,0 +1,5 @@ +CPU Control Registers +======================= + +.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/control_register.hpp + diff --git a/docs/arch/x86_64/memory/cpu/msr.rst b/docs/arch/x86_64/memory/cpu/msr.rst new file mode 100644 index 0000000..c67d51c --- /dev/null +++ b/docs/arch/x86_64/memory/cpu/msr.rst @@ -0,0 +1,5 @@ +CPU Model-Specific Register +======================= + +.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/msr.hpp + diff --git a/docs/arch/x86_64/memory/cpu/tlb.rst b/docs/arch/x86_64/memory/cpu/tlb.rst new file mode 100644 index 0000000..0d482dc --- /dev/null +++ b/docs/arch/x86_64/memory/cpu/tlb.rst @@ -0,0 +1,5 @@ +CPU Translation Lookaside Buffer +======================= + +.. doxygenfile:: arch/x86_64/include/arch/memory/cpu/tlb.hpp + |